4
LTC1255
CCHARA TERIST
ICS
UW
AT
Y
P
I
CA
LPER
F
O
R
C
E
Input Threshold Voltage
Short-Circuit Turn-OFF Delay TimeTurn-ON Time
Standby Supply Current
Supply Current per Channel (ON)
Input ON Threshold
Gate Clamp CurrentDrain Sense Threshold Voltage
Turn-OFF Time
SUPPLY VOLTAGE (V)
0
0.4
INPUT THRESHOLD VOLTAGE (V)
0.8
1.0
1.2
1.4
1.6
1.8
5
10
15 20
LTC1255 • TPC04
25
2.0
2.2
2.4
0.6
30
V
ON
V
OFF
SUPPLY VOLTAGE (V)
0
75
DRAIN SENSE THRESHOLD VOLTAGE (V)
85
90
95
100
105
110
5
10
15 20
LTC1255 • TPC05
25
115
120
125
80
30
T
A
= 25°C
SUPPLY VOLTAGE (V)
0
0
GATE CLAMP CURRENT (µA)
10
15
20
25
30
35
5
10
15 20
LTC1255 • TA06
25
40
45
50
5
30
V
CLAMP
= 12V
T
A
= 25°C
SUPPLY VOLTAGE (V)
0
0
TURN-ON TIME (µs)
200
300
400
500
600
700
5
10
15 20
LTC1255 • TA07
25
800
900
1000
100
30
C
GATE
= 1000pF
T
A
= 25°C
V
GS
= 5V
V
GS
= 2V
SUPPLY VOLTAGE (V)
0
0
TURN-OFF TIME (µs)
10
15
20
25
30
35
5
10
15 20
LTC1255 • TA08
25
40
45
50
5
30
C
GATE
= 1000pF
TIME FOR V
GATE
< 1V
SUPPLY VOLTAGE (V)
0
0
TURN-OFF TIME (µs)
10
15
20
25
30
35
5
10
15 20
LTC1255 • TA09
25
40
45
50
5
30
C
GATE
= 1000pF
TIME FOR V
GATE
< 1V
TEMPERATURE (°C)
–50
0
STANDBY SUPPLY CURRENT (µA)
10
15
20
25
30
35
–25
0
25 50
LTC1255 • TA10
75
40
45
50
5
100
V
S
= 10V
V
S
= 18V
V
S
= 24V
TEMPERATURE (°C)
–50
0.4
INPUT THRESHOLD VOLTAGE (V)
0.8
1.0
1.2
1.4
1.6
1.8
–25
0
25 50
LTC1255 • TA12
75
2.0
2.2
2.4
0.6
100
V
S
= 10V
V
S
= 24V
TEMPERATURE (°C)
–50
0
SUPPLY CURRENT (mA)
0.4
0.6
0.8
1.0
1.2
1.4
–25
0
25 50
LTC1255 • TA11
75
1.6
1.8
2.0
0.2
100
V
S
= 24V
V
S
= 10V
V
S
= 18V
5
LTC1255
PI FU CTIO S
U
UU
Input Pin
The LTC1255 input pin is active high and activates all of
the protection and charge pump circuitry when switched
ON. The LTC1255 logic and shutdown inputs are high
impedance CMOS gates with ESD protection diodes to
ground and supply and therefore should not be forced
beyond the power supply rails. The input pin should be
held low during the application of power to properly set
the input latch.
Gate Drive Pin
The gate drive pin is either driven to ground when the
switch is turned OFF or driven above the supply rail
when the switch is turned ON. This pin is of relatively
high impedance when driven above the rail (the equiva-
lent of a few hundred k). Care should be taken to
minimize any loading of this pin by parasitic resistance
to ground or supply.
Supply Pin
The supply pin of the LTC1255 serves two vital pur-
poses. The first is obvious; it powers the input, gate
drive, regulation and protection circuitry. The second
purpose is less obvious; it provides a Kelvin connection
to the top of the drain sense resistor for the internal
100mV reference.
The supply pin of the LTC1255 should never be forced
below ground as this may result in permanent damage
to the device
. A 100 resistor should be inserted in
series with the ground pin if negative supply voltage
transients are anticipated.
The LTC1255 is designed to be continuously powered
so that the gate of the MOSFET is actively driven at all
times. If it is necessary to remove power from the
supply pin and then reapply it, the input pin should be
cycled (low to high) a few milliseconds
after
the power
is reapplied to reset the input latch and protection
circuitry. Also, the input pin should be isolated from the
controlling logic by a 10k resistor if there is a possibility
that the input pin will be held high after the supply has
been removed.
Drain Sense Pin
The drain sense pin is compared against the supply pin
voltage. If the voltage at this pin is more than 100mV
below the supply pin, the input latch will be reset and
the MOSFET gate will be quickly discharged. Cycle the
input to reset the short-circuit latch and turn the MOSFET
back on.
This pin is also a high impedance CMOS gate with ESD
protection and therefore should not be forced outside
of the power supply rails. To defeat the overcurrent
protection, short the drain sense pin to the supply pin.
Some loads, such as large supply capacitors, lamps or
motors require high in-rush currents. An RC time delay
can be added between the sense resistor and the drain
sense pin to ensure that the drain sense circuitry does
not false trigger during startup. This time constant can
be set from a few microseconds to many seconds.
However, very long delays may put the MOSFET at risk
of being destroyed by a short-circuit condition (see
Applications Information section).
OPERATIO
U
The LTC1255 is a dual 24V MOSFET driver with built-in
protection and gate charge pump. The LTC1255 consists
of the following functional blocks:
TTL and CMOS Compatible Inputs and Latches
The LTC1255 inputs have been designed to accommo-
date a wide range of logic families. Both input thresh-
olds are set at about 1.3V with approximately 100mV of
hysteresis. A low standby current regulator provides
continuous bias for the TTL-to-CMOS converter.
The input/protection latch should be set after initial
power-up, or after reapplication of power, by cycling
the input low to high.
6
LTC1255
OPERATIO
U
Internal Voltage Regulation
The output of the TTL-to-CMOS converter drives two
regulated supplies which power the low voltage CMOS
logic and analog blocks. The regulator outputs are isolated
from each other so that the noise generated by the charge
pump logic is not coupled into the 100mV reference or the
analog comparator.
Gate Charge Pump
Gate drive for the power MOSFET is produced by an
adaptive charge pump circuit which generates a gate
voltage substantially higher than the power supply volt-
age. The charge pump capacitors are included on-chip and
therefore no external components are required to generate
the gate drive. The charge pump is designed to drive a 12V
Zener diode clamp connected across the gate and source
of the MOSFET switch.
(One Channel)
BLOCK DIAGRA
W
Drain Current Sense
The LTC1255 is configured to sense the current flowing
into the drain of the power MOSFET in a high-side applica-
tion. An internal 100mV reference is compared to the drop
across a sense resistor (typically 0.002 to 0.10) in
series with the drain lead. If the drop across this resistor
exceeds the internal 100mV threshold, the input latch is
reset and the gate is quickly discharged via a relatively
large N-channel transistor.
Controlled Gate Rise and Fall Times
When the input is switched ON and OFF, the gate is
charged by the internal charge pump and discharged in a
controlled manner. The charge and discharge rates have
been set to minimize RFI and EMI emissions in normal
operation. If a short circuit or current overload condition
is encountered, the gate is discharged very quickly (typi-
cally a few microseconds) by a large N-channel transistor.
100mV
REFERENCE
10µs
DELAY
LOW STANDBY
CURRENT
REGULATOR
TTL-TO-CMOS
CONVERTER
VOLTAGE
REGULATOR
ANALOG DIGITAL
INPUT
LATCH
R
S
ONE
SHOT
OSCILLATOR
AND CHARGE
PUMP
GATE CHARGE
AND DISCHARGE
CONTROL LOGIC
FAST/SLOW
GATE CHARGE
LOGIC
INPUT
GATE
DRAIN
SENSE
ANALOG SECTION
COMP
GND
V
S
LTC1255 • BD

LTC1255CN8#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Gate Drivers 2x 24V Hi-Side MOSFET Drvr
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union