Evaluation Board User Guide UG-366
Rev. A | Page 11 of 16
PCB LAYOUT GUIDELINES
1. Use separate analog and power ground planes. Connect the
analog circuitry to analog ground. Connect the power
circuitry to power ground.
2. To keep the inductance down, the traces from the high-
side MOSFET and the low-side MOSFET to the DH and
DL pins of the ADP1822, respectively, need to be relatively
short and wide.
3. Place the source of Q1 and the drain of Q2 very close to
each other to minimize inductance. Use a wide copper
trace for this connection. However, too much copper area
on this switch node can increase capacitive-coupled
common-mode noise.
4. Place ceramic input decoupling capacitors (C2, C3, and
C4) close to the Q1 drain and the Q2 source.
5. Place C13 and C14 close to the V
IN
pin of the IC.
6. The compensation components should also be placed as
close as possible to the FB pin.
7. Connect the trace connecting R7 should be directly to the
drain of Q2 to ensure an ideal Kelvin connection,.
