Evaluation Board User Guide UG-366
Rev. A | Page 5 of 16
t
R
and t
F
can be calculated using
G
SPG
GD
GS
R
R
VV
Q
Q
t
−
+
=
2
and
G
SP
GD
GS
F
R
V
Q
Q
t
+
=
2
where:
Q
GS
and Q
GD
are provided in the MOSFET data sheet.
R
G
is the gate resistance
V
SP
is approximated using
where g
m
is the MOSFET transconductance.
The high-side MOSFET conduction loss can be calculated as
DSON
L
OUT
highC
R
I
IDP
∆
+=
12
2
2
,
(9)
OUTPUT VOLTAGE
The regulation threshold at the FB pin is 0.6 V, and th e
maximum input bias current is 100 nA. This bias current can
introduce significant error if the divider impedance is too high.
In order to get the best accuracy, the bottom resistor, R2, should
be no higher than 50 kΩ. On the other hand, very low values of
R2 will dissipate excess power. For R2, a 1% resistor with a value
between 1 kΩ and 10 kΩ is recommended.
The upper divider is then set using the following formula (it
should also be a 1% type):
(10)
CURRENT LIMIT SET RESISTOR
The voltage on the CSL pin can be calculated by the following
formula:
( )
lowDSON
L
L
lowDSON
CSLCSL
CSL
R
I
IRRIV
__
2
∆
+−+=
(11)
where:
V
CSL
is the voltage on the CSL pin.
I
CSL
is the current out from the CSL pin, I
CSL
= 42 μA.
R
CSL
is the current limited resistor.
R
DSON _low
is the conduction resistor of the lower side MOSFET.
I
L
is the output current.
ΔI
L
is the output current ripple.
In normal operation, the direction of current flow through the
low-side FET causes a negative voltage to appear on its drain.
This voltage is V = IR, where I is the instantaneous FET current
and R is its R
DSON
. A +42 μA current source at the ADP1822
CSL pin causes a fixed voltage drop in the current sense resistor
that is connected from the CSL pin to the drain of the low-side
FET. This current through the current limit set resistor produces
a voltage in the opposite direction, thus raising (in the positive
direction) the potential at the CSL pin. The resulting net voltage
on the CSL pin is compared with ground. During normal
operation, the CSL pin stays above ground potential. The
overcurrent protection circuitry is triggered when increased
FET current produces increased negative voltage on the low-
side MOSFET drain, thus causing the voltage on the CSL pin to
go negative with respect to ground.
Therefore, the resistor R
CSL
can be calculated from the following
equation:
CSL
lowDSON
L
CSL
I
R
I
I
R
_
2
∆
+
=
limit
(12)
SETTING THE SOFT START
The soft start characteristic is set by the capacitor connected
from SS to GND. The ADP1822 charges C
SS
to 0.8 V through an
internal resistor. The soft start period (t
SS
) is achieved when
V
CSS
= 0.6 V.
kΩ100
8.0
6.0
1ln ×
−−
=
SS
SS
t
C
(13)
where 100 kΩ is the internal resistor.
OUTPUT VOLTAGE TRACKING
The ADP1822 features an internal comparator that forces the
output voltage to track an external voltage at startup, which
prevents the output voltage from exceeding the tracking voltage.
The comparator turns off the high-side switch if the positive
tracking (TRKP) input voltage exceeds the negative tracking
(TRKN) input voltage. Connect TRKP to the output voltage and
drive TRKN with the voltage to be tracked. If the voltage at
TRKN is below the regulation voltage, the output voltage at
TRKN is below the regulation voltage, and the output voltage is
limited to the voltage at TRKN. If the voltage at TRKN is above
the regulation voltage, the output voltage regulates the desired
voltage set by the voltage divider.
