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IS62C256AL-25ULI-TR

P1-P3P4-P6P7-P9P10-P12
Integrated Silicon Solution, Inc. 7
Rev. E
07/20/2015
IS65C256AL
IS62C256AL
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(OverOperatingRange)
-25 ns -45 ns
Symbol Parameter Min. Max. Min. Max. Unit
twc WriteCycleTime 25 — 45 — ns
tscs CEtoWriteEnd 15 — 35 — ns
taw AddressSetupTimetoWriteEnd 15 — 25 — ns
tha AddressHoldfromWriteEnd 0 — 0 — ns
tsa AddressSetupTime 0 — 0 — ns
tPwe
(4)
WEPulseWidth 15 — 25 — ns
tsd DataSetuptoWriteEnd 12 — 20 — ns
thd DataHoldfromWriteEnd 0 — 0 — ns
thzwe
(2)
WELOWtoHigh-ZOutput — 8 — 20 ns
tlzwe
(2)
WEHIGHtoLow-ZOutput 0 — 0 — ns
Notes:
1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof1.5V,inputpulselevelsof0to3.0Vand
outputloadingspeciedinFigure1.
2. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
3. TheinternalwritetimeisdenedbytheoverlapofCELOWandWELOW.AllsignalsmustbeinvalidstatestoinitiateaWrite,
butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtotherisingorfalling
edge of the signal that terminates the write.
4. TestedwithOE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1
(CE Controlled, OEisHIGHorLOW)
(1)
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCS
t
PWE
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
CS_WR1.eps
8 Integrated Silicon Solution, Inc.
Rev. E
07/20/2015
IS65C256AL
IS62C256AL
AC WAVEFORMS
WRITE CYCLE NO. 2
(OE isHIGHDuringWriteCycle)
(1,2)
WRITE CYCLE NO. 3
(OE isLOWDuringWriteCycle)
(1)
Notes:
1. TheinternalwritetimeisdenedbytheoverlapofCELOWandWELOW.AllsignalsmustbeinvalidstatestoinitiateaWrite,
butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtotherisingorfalling
edge of the signal that terminates the write.
2. I/OwillassumetheHigh-ZstateifOE =
VIh.
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
DIN
OE
DATA
IN
VALID
t
LZWE
t
SD
CS_WR2.eps
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CS_WR3.eps
Integrated Silicon Solution, Inc. 9
Rev. E
07/20/2015
IS65C256AL
IS62C256AL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Min. Typ. Max. Unit
VdrVddforDataRetention SeeDataRetentionWaveform 2.0 5.5 V
Idr DataRetentionCurrent Vdd=2.0V,CE ≥Vdd–0.2V Com. — — 15 µA
VIn ≥ Vdd – 0.2V, or VIn
≤
Vss + 0.2V
Ind. — — 20
Auto. — — 50
tsdr DataRetentionSetupTime SeeDataRetentionWaveform 0 — ns
trdr RecoveryTime SeeDataRetentionWaveform trc — ns
Note:
1.TypicalValuesaremeasuredatVdd=5V,Ta = 25
o
Candnot100%tested.
DATA RETENTION WAVEFORM (CE Controlled)
VDD
CE1 ≥ VDD
- 0.2V
t
SDR
t
RDR
V
DR
CE1
GND
4.5V
2.2V
Data Retention Mode
P1-P3P4-P6P7-P9P10-P12

IS62C256AL-25ULI-TR

Mfr. #:
Buy IS62C256AL-25ULI-TR
Manufacturer:
ISSI
Description:
SRAM 256K (32K x 8) 25ns Async SRAM 5v
Lifecycle:
New from this manufacturer.
Delivery:
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