41
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT INDUSTRIAL TEMPERATURE RANGES
4.2 JTAG DATA REGISTER
4.2.1 DEVICE IDENTIFICATION REGISTER (IDR)
The IDR can be set to define the producer number, part number and
the device revision, which can be used to verify the proper version or
revision number that has been used in the system under test. The IDR is
32 bits long and is partitioned as in Table-20. Data from the IDR is
shifted out to TDO LSB first.
4.2.2 BYPASS REGISTER (BR)
The BR consists of a single bit. It can provide a serial path between
the TDI input and TDO output, bypassing the BSR to reduce test access
times.
4.2.3 BOUNDARY SCAN REGISTER (BSR)
The BSR can apply and read test patterns in parallel to or from all the
digital I/O pins. The BSR is a 98 bits long shift register and is initialized
and read using the instruction EXTEST or SAMPLE/PRELOAD. Each
pin is related to one or more bits in the BSR. Please refer to Table-21 for
details of BSR bits and their functions.
Table-19 Instruction Register Description
IR Code Instruction Comments
000 Extest
The external test instruction allows testing of the interconnection to other devices. When the current instruction is the
EXTEST instruction, the boundary scan register is placed between TDI and TDO. The signal on the input pins can be
sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by
shifting the boundary scan register using the Shift-DR state. The signal on the output pins can be controlled by loading
patterns shifted in through input TDI into the boundary scan register using the Update-DR state.
100 Sample/Preload
The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed
between TDI and TDO. The normal path between
IDT82V2048 logic and the I/O pins is maintained. Primary device
inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled val-
ues can then be viewed by shifting the boundary scan register using the Shift-DR state.
110 Idcode
The identification instruction is used to connect the identification register between TDI and TDO. The device's identifica-
tion code can then be shifted out using the Shift-DR state.
111 Bypass
The bypass instruction shifts data from input TDI to output TDO with one TCK clock period delay. The instruction is used
to bypass the device.
Table-20 Device Identification Register Description
Bit No. Comments
0Set to ‘1’
1~11 Producer Number
12~27 Part Number
28~31 Device Revision
Table-21 Boundary Scan Register Description
Bit No. Bit Symbol Pin Signal Type Comments
0POUT0LP0 I/O
1PIN0LP0I/O
2POUT1LP1 I/O
3PIN1LP1I/O
4POUT2LP2 I/O
5PIN2LP2I/O
6POUT3LP3 I/O
7PIN3LP3I/O
8POUT4LP4 I/O
9PIN4LP4I/O
10 POUT5 LP5 I/O
11 PIN5 LP5 I/O
12 POUT6 LP6 I/O
13 PIN6 LP6 I/O
14 POUT7 LP7 I/O
15 PIN7 LP7 I/O
