MAX7310
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
4 _______________________________________________________________________________________
Typical Operating Characteristics
(T
A
= +25°C, unless otherwise noted.)
4
5
7
6
8
9
-40 -10 5 20-25 35 50 65 80 95 110 125
I/O1–I/O7 OUTPUT SOURCE CURRENT
vs. TEMPERATURE
MAX7310 toc06
TEMPERATURE (°C)
SOURCE CURRENT (mA)
V+ = 2.3V,
V
OH
= 1.4V
0
15
10
5
25
20
30
35
2.0 3.0 3.5 4.02.5 4.5 5.0 5.5
I/O0–I/O7 OUTPUT SINK CURRENT
vs. SUPPLY VOLTAGE
MAX7310 toc05
SUPPLY VOLTAGE (V)
SINK CURRENT (mA)
V
OL
= 0.5V
0
10
5
20
15
25
30
-40 -10 5 20-25 35 50 65 80 95 110 125
I/O0–I/O7 OUTPUT SINK CURRENT
vs. TEMPERATURE
MAX7310 toc04
TEMPERATURE (°C)
SINK CURRENT (mA)
V
OL
= 0.5V
V
CC
= 3.3V
V
CC
= 2.3V
10
40
20
60
70
2.0 3.0 3.5 4.02.5 4.5 5.0 5.5
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX7310 toc03
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
30
50
f
SCL
= 440kHz,
NO LOAD ON I/O0–I/O7
1.00
1.50
1.25
2.00
1.75
2.25
2.50
-40 -10 5 20-25 35 50 65 80 95 110 125
STANDBY SUPPLY CURRENT
vs. TEMPERATURE
MAX7310 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
V+ = 3.3V, f
SCL
= 0,
NO LOAD ON I/O0–I/O7
26
28
27
30
29
31
32
-40 -10 5 20-25 35 50 65 80 95 110 125
SUPPLY CURRENT
vs. TEMPERATURE
MAX7310 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
V+ = 3.3V, f
SCL
= 440kHz,
NO LOAD ON I/O0–I/O7
Detailed Description
The MAX7310 general-purpose input/output (GPIO)
peripheral provides up to eight I/O ports, controlled
through an I
2
C-compatible serial interface. The
MAX7310 consists of an input port register, an output
port register, a polarity inversion register, a configura-
tion register, and a bus timeout register. An active-low
reset input sets the eight I/O lines as inputs. Three
slave ID address select pins (AD0, AD1, and AD2)
choose one of 56 slave ID addresses (Figure 1).
MAX7310
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
_______________________________________________________________________________________________________ 5
Pin Description
PIN
TSSOP/
QSOP
THIN
QFN
NAME FUNCTION
1 15 SCL Serial Clock Line
2 16 SDA Serial Data Line
3 1 AD0 Address Input 0
4 2 AD1 Address Input 1
5 3 AD2 Address Input 2
6 4 I/O0 Input/Output Port 0 (Open Drain)
7 5 I/O1 Input/Output Port 1
8 6 GND Supply Ground
9–14 7–12 I/O2–I/O7 Input/Output Port 2—Input/Output Port 7
15 13 RESET
External Reset (Active Low). Pull RESET low to configure I/O pins as inputs. Set RESET
high for normal operation.
16 14 V+ Supply Voltage. Bypass with a 0.047µF capacitor to GND.
PAD
Exposed
pad
Exposed Pad on Package Underside. Connect to GND.
Figure 1. MAX7310 Block Diagram
AD0
AD1
AD2
SCL
SDA
SMBus
CONTROL
INPUT
FILTER
POWER-ON
RESET
RESET
GND
V+
INPUT/
OUTPUT
PORTS
WRITE PULSE
READ PULSE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
8 BIT
N
MAX7310
MAX7310
Table 1 is the register address table. Tables 2–6 list
register 0 through register 4 information.
Serial Interface
Serial Addressing
The MAX7310 operates as a slave that sends and
receives data through a 2-wire interface. The interface
uses a serial data line (SDA) and a serial clock line
(SCL) to achieve bidirectional communication between
master(s) and slave(s). A master, typically a microcon-
troller, initiates all data transfers to and from the
MAX7310, and generates the SCL clock that synchro-
nizes the data transfer (Figure 2).
Each transmission consists of a start condition sent by
a master, followed by the MAX7310 7-bit slave address
plus an R/W bit, a register address byte, one or more
data bytes, and finally a stop condition (Figure 3).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a start (S) condition by transitioning SDA from
high to low while SCL is high. When the master has fin-
ished communicating with the slave, it issues a stop (P)
condition by transitioning SDA from low to high while
SCL is high. The bus is then free for another transmis-
sion (Figure 3).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
Acknowledge
The acknowledge bit is a clocked 9th bit, which the
recipient uses as a handshake receipt of each byte of
data (Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high period of the clock pulse. When
the master is transmitting to the MAX7310, the
MAX7310 generates the acknowledge bit since the
MAX7310 is the recipient. When the MAX7310 is trans-
mitting to the master, the master generates the
acknowledge bit.
Slave Address
The MAX7310 has a 7-bit-long slave address (Figure
6). The 8th bit following the 7-bit slave address is the
R/W bit. Set this bit low for a write command and high
for a read command.
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
6 _______________________________________________________________________________________
Figure 2. 2-Wire Serial Interface Timing Diagrams
SCL
SDA
START CONDITIONSTOP CONDITION
REPEATED START CONDITION
START CONDITION
t
SU, DAT
t
HD, DAT
t
LOW
t
HD, STA
t
HIGH
t
R
t
F
t
SU, STA
t
HD, STA
t
SU, STO
t
BUF
Figure 3. Start and Stop Conditions
SDA
SCL
S
START
CONDITION
P
STOP
CONDITION

MAX7310ATE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Interface - I/O Expanders 8-Bit I/O Port Expander
Lifecycle:
New from this manufacturer.
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