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CAV25640VE-GT3

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
CAT25640
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7
Status Register
The Status Register, as shown in Table 10, contains a
number of status and control bits.
The RDY
(Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1 during
an internal write cycle, and reset to 0 when the device is ready
to accept commands. For the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 11. The protected
blocks then become read−only.
The WPEN (Write Protect Enable) bit acts as an enable for
the WP
pin. Hardware write protection is enabled when the
WP
pin is low and the WPEN bit is 1. This condition
prevents writing to the status register and to the block
protected sections of memory. While hardware write
protection is active, only the non−block protected memory
can be written. Hardware write protection is disabled when
the WP
pin is high or the WPEN bit is 0. The WPEN bit, WP
pin and WEL bit combine to either permit or inhibit Write
operations, as detailed in Table 12.
Table 10. STATUS REGISTER
7 6 5 4 3 2 1 0
WPEN 0 0 0 BP1 BP0 WEL RDY
Table 11. BLOCK PROTECTION BITS
Status Register Bits
Array Address Protected Protection
BP1 BP0
0 0 None No Protection
0 1 1800−1FFF Quarter Array Protection
1 0 1000−1FFF Half Array Protection
1 1 0000−1FFF Full Array Protection
Table 12. WRITE PROTECT CONDITIONS
WPEN WP WEL Protected Blocks Unprotected Blocks Status Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable
CAT25640
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8
WRITE OPERATIONS
The CAT25640 device powers up into a write disable
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the memory
array or to the status register. In addition, the address of the
memory location(s) to be written must be outside the
protected area, as defined by BP0 and BP1 bits from the
status register.
Write Enable and Write Disable
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
instruction to the CAT25640. Care must be taken to take the
CS
input high after the WREN instruction, as otherwise the
Write Enable Latch will not be properly set. WREN timing
is illustrated in Figure 3. The WREN instruction must be
sent prior to any WRITE or WRSR instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
Figure 3. WREN Timing
SCK
SI
SO
00000
110
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
CS
Figure 4. WRDI Timing
SCK
SI
SO
00000
100
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
CS
CAT25640
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9
Byte Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 16−bit address
and data as shown in Figure 5. Only 13 significant address
bits are used by the CAT25640. The rest are don’t care bits,
as shown in Table 13. Internal programming will start after
the low to high CS
transition. During an internal write cycle,
all commands, except for RDSR (Read Status Register) will
be ignored. The RDY
bit will indicate if the internal write
cycle is in progress (RDY
high), or the device is ready to
accept commands (RDY
low).
Page Write
After sending the first data byte to the CAT25640, the host
may continue sending data, up to a total of 64 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following completion of the write cycle, the CAT25640 is
automatically returned to the write disable state.
Table 13. BYTE ADDRESS
Device Address Significant Bits Address Don’t Care Bits # Address Clock Pulses
CAT25640 A12 − A0 A15 − A13 16
Figure 5. Byte WRITE Timing
SCK
SI
SO
0000 01 0
D7 D6 D5 D4 D3 D2 D1 D0
012345678
OPCODE
DATA IN
HIGH IMPEDANCE
BYTE ADDRESS*
21 22 23 24 25 26 27 28 29 30 31
Dashed Line = mode (1, 1)
CS
A
0
A
N
0
* Please check the Byte Address Table (Table 13)
Figure 6. Page WRITE Timing
SCK
SI
SO
0000 0 10
BYTE ADDRESS*
Data
Byte 1
012345678 212223
24−31
32−39
Data Byte N
OPCODE
7..1 0
24+(N−1)x8−1 .. 24+(N−1)x8
24+Nx8−1
DATA IN
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
CS
A
N
A
0
Data
Byte 3
Data
Byte 2
0
* Please check the Byte Address Table (Table 13)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

CAV25640VE-GT3

Mfr. #:
Buy CAV25640VE-GT3
Manufacturer:
ON Semiconductor
Description:
EEPROM 64KB SPI SER CMOS EEPROM
Lifecycle:
New from this manufacturer.
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