OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

74ALVC162334ADGG:5

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
74ALVC162334A_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 13 December 2006 4 of 19
NXP Semiconductors
74ALVC162334A
16-bit registered driver (3-state)
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 4. Pin configuration for TSSOP48
74ALVC162334ADGG
OE CP
Y1 A1
Y2 A2
GND GND
Y3 A3
Y4 A4
V
CC
V
CC
Y5 A5
Y6 A6
GND GND
Y7 A7
Y8 A8
Y9 A9
Y10 A10
GND GND
Y11 A11
Y12 A12
V
CC
V
CC
Y13 A13
Y14 A14
GND GND
Y15 A15
Y16 A16
n.c. LE
002aac722
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Table 3. Pin description
Symbol Pin Description
OE 1 output enable input (active LOW)
Y1 2 data output 1
Y2 3 data output 2
GND 4, 10, 15, 21,
28, 34, 39, 45
ground supply (0 V)
Y3 5 data output 3
Y4 6 data output 4
V
CC
7, 18, 31, 42 positive supply voltage
Y5 8 data output 5
Y6 9 data output 6
Y7 11 data output 7
Y8 12 data output 8
74ALVC162334A_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 13 December 2006 5 of 19
NXP Semiconductors
74ALVC162334A
16-bit registered driver (3-state)
Y9 13 data output 9
Y10 14 data output 10
Y11 16 data output 11
Y12 17 data output 12
Y13 19 data output 13
Y14 20 data output 14
Y15 22 data output 15
Y16 23 data output 16
n.c. 24 not connected
LE 25 latch enable input (active LOW)
A16 26 data input 16
A15 27 data input 15
A14 29 data input 14
A13 30 data input 13
A12 32 data input 12
A11 33 data input 11
A10 35 data input 10
A9 36 data input 9
A8 37 data input 8
A7 38 data input 7
A6 40 data input 6
A5 41 data input 5
A4 43 data input 4
A3 44 data input 3
A2 46 data input 2
A1 47 data input 1
CP 48 clock input
Table 3. Pin description
…continued
Symbol Pin Description
74ALVC162334A_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 13 December 2006 6 of 19
NXP Semiconductors
74ALVC162334A
16-bit registered driver (3-state)
7. Functional description
Refer to Figure 1 “Logic symbol (IEEE/IEC)” and Figure 2 “Logic diagram”.
7.1 Function selection
[1] Output level before the indicated steady-state input conditions were established, provided that CP is HIGH
before LE goes LOW.
[2] Output level before the indicated steady-state input conditions were established.
Table 4. Function selection
H = HIGH voltage level; L = LOW voltage level; X = Don’t care; Z = high-impedance OFF-state;
↑
= LOW to HIGH level transition.
Inputs Outputs
OE LE CP An Yn
HXXXZ
LLXLL
LLXHH
LH↑ LL
LH↑ HH
LHHXY
0
[1]
LHLXY
0
[2]
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

74ALVC162334ADGG:5

Mfr. #:
Buy 74ALVC162334ADGG:5
Manufacturer:
Description:
IC UNIV BUS DVR 16BIT 48TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet