Advanced Clock Drivers Devices
6 Freescale Semiconductor
MPC9446
APPLICATIONS INFORMATION
Driving Transmission Lines
The MPC9446 clock driver was designed to drive high-
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 Ω, the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale application note
AN1091. In most high performance clock networks,
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50 Ω resistance to V
CC
÷2.
This technique draws a fairly high level of DC current, and
thus, only a single terminated line can be driven by each
output of the MPC9446 clock driver. For the series terminated
case, however, there is no DC current draw; thus, the outputs
can drive multiple series terminated lines. Figure 3 illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme,
the fanout of the MPC9446 clock driver is effectively doubled
due to its capability to drive multiple lines.
Figure 3. Single versus Dual Transmission Lines
The waveform plots in Figure 4 show the simulation
results of an output driving a single line versus two lines. In
both cases, the drive capability of the MPC9446 output buffer
is more than sufficient to drive 50 Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9446. The output waveform
in Figure 4 shows a step in the waveform. This step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 36 Ω series resistor plus the
output impedance does not match the parallel combination of
the line impedances. The voltage wave launched down the
two lines will equal:
V
L
=V
S
(Z
0
÷ (R
S
+ R
0
+ Z
0
))
Z
0
= 50 Ω || 50 Ω
R
S
= 36 Ω || 36 Ω
R
0
= 14 Ω
V
L
= 3.0 (25 ÷ (18 + 14 + 25)
= 1.31 V
At the load end, the voltage will double, due to the near
unity reflection coefficient, to 2.5 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
Figure 4. Single versus Dual Waveforms
Since this step is well above the threshold region, it will not
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines, the
situation in Figure 5 should be used. In this case, the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance, the line
impedance is perfectly matched.
Figure 5. Optimized Dual Line Termination
14Ω
IN
MPC9446
Output
Buffer
R
S
= 36Ω
Z
O
= 50Ω
OutA
14Ω
IN
MPC9446
Output
Buffer
R
S
= 36Ω
Z
O
= 50Ω
OutB0
R
S
= 36Ω
Z
O
= 50Ω
OutB1
Voltage (V)
OutB
t
D
= 3.9386
OutA
t
D
= 3.8956
In
246 8101214
Time (ns)
3.0
2.5
2.0
1.5
1.0
0.5
0
Z
O
= 50Ω
Z
O
= 50Ω
14Ω
MPC9446
Output
Buffer
R
S
= 22Ω
R
S
= 22Ω
14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω
25 Ω = 25 Ω
