Advanced Clock Drivers Devices
Freescale Semiconductor 7
MPC9446
Figure 6. CCLK0, 1 MPC9446 AC Test Reference for V
CC
= 3.3 V and V
CC
= 2.5 V
Figure 7. Output Transition Time Test Reference
Figure 8. Propagation Delay (t
PD
) Test Reference
Figure 9. Output-to-Output Skew t
SK(LH, HL)
Figure 10. Output Pulse Skew (t
SK(P)
) Test Reference
Figure 11. Output Duty Cycle (DC)
Figure 12. Cycle-to-Cycle Jitter
Pulse
Generator
Z = 50Ω
R
T
= 50Ω
Z
O
= 50Ω
R
T
= 50Ω
Z
O
= 50 Ω
MPC9446 DUT
V
TT
V
TT
V
CC
= 3.3V V
CC
= 2.5V
2.4 1.8V
0.55 0.6V
t
F
t
R
t
(LH)
V
CC
V
CC
÷2
GND
V
CC
V
CC
÷2
GND
CCLK
Qx
t
(HL)
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any two similar delay paths
within a single device.
V
CC
V
CC
÷2
GND
V
CC
V
CC
÷2
GND
t
SK(LH)
t
SK(HL)
V
CC
V
CC
÷2
GND
V
CC
V
CC
÷2
GND
t
(LH)
CCLK
Q
X
t
(HL)
t
SK(P)
= | t
PLH
– t
PHL
|
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage.
V
CC
V
CC
÷2
GND
t
P
T
0
DC = t
P
/T
0
x 100%
The variation in cycle time of a signal between adjacent
cycles, over a random sample of adjacent cycle pairs.
T
N
T
JIT(CC)
= |T
N
-T
N+1
|
T
N+1
