TPD2EUSB30DRTR

© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 4
1 Publication Order Number:
ESD8040/D
ESD8040
ESD Protection Diode
Low Capacitance Array for High Speed
Video Interfaces
The ESD8040 is designed specifically to protect HDMI and Display
Port Interfaces with full functionality ESD protection and back drive
current protection for V
CC
line. Ultra−low capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines. The flow−through style
package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance for the high speed TMDS
lines.
Features
Full Function HDMI / Display Port Solution
Single Connect, Flow through Routing for TMDS Lines
Low Capacitance (0.35 pF Max, I/O to GND)
Protection for the Following IEC Standards:
IEC 61000−4−2 Level 4
UL Flammability Rating of 94 V−0
This is a Pb−Free Device
Typical Applications
HDMI 1.3/1.4/2.0
Display Port
MAXIMUM RATINGS (T
J
= 25°C unless otherwise noted)
Rating
Symbol Value Unit
Operating Junction Temperature Range T
J
55 to +125 °C
Storage Temperature Range T
stg
55 to +150 °C
Lead Solder Temperature −
Maximum (10 Seconds)
T
L
260 °C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ESD
ESD
±15
±15
kV
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
MARKING
DIAGRAM
Device Package Shipping
ORDERING INFORMATION
UDFN18
CASE 517CP
www.onsemi.com
ESD8040MUTAG UDFN18
(Pb−Free)
3000 / Tape & Ree
l
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
(Note: Microdot may be in either location)
8040MG
G
8040 = Specific Device Code
M = Date Code
G = Pb−Free Package
1
18
ESD8040
www.onsemi.com
2
Pin 1 Pin 2 Pin 3
Pin 4 Pin 5 Pin 6
Pin 7 Pin 8 Pin 9
Pin 10 Pin 11 Pin 13 Pin 15 Pin 17
Center Pins, Pin 12, 14, 16, 18
Note: Common GND – Only minimum of 1 GND connection required
Figure 1. Pin Schematic
Figure 2. Pin Configuration
=
Note: Pins 12, 14, 16, 18 and center pins are connected internally as a common ground.
Only minimum of one pin needs to be connected to ground for functionality of all pins.
1
2
3
4
5
6
7
8
9
10
11
18
17
16
15
14
13
12
GND
GND
GND
GND
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
=
TMDS I/O Pins 1, 2, 4, 5, 7, 8, 10, 11 Non−TMDS I/O Pins 3, 6, 9, 13, 15, 17
ESD8040
www.onsemi.com
3
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
I
PP
Maximum Peak Pulse Current
V
C
Clamping Voltage @ I
PP
V
RWM
Working Peak Reverse Voltage
I
R
Maximum Reverse Leakage Current @ V
RWM
V
BR
Breakdown Voltage @ I
T
I
T
Test Current
R
DYN
Dynamic Resistance
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
Uni−Directional TVS
I
PP
I
PP
V
I
I
R
I
T
V
RWM
V
CL
V
BR
V
CL
R
DYN
R
DYN
ELECTRICAL CHARACTERISTICS (T
A
= 25°C unless otherwise specified)
Parameter Symbol Conditions Min Typ Max Unit
Reverse Working Voltage V
RWM
I/O Pin to GND 3.3 V
Breakdown Voltage V
BR
I
T
= 1 mA, I/O Pins 1, 2, 4, 5, 7, 8, 10, 11 to GND
I
T
= 1 mA, I/O Pins 3, 6, 9, 13, 15, 17 to GND
4.0
5.5
5.5
6.5
V
Reverse Leakage Current I
R
V
RWM
= 3.3 V, I/O Pin to GND 1.0
mA
Clamping Voltage (Note 1) V
C
IEC61000−4−2, ±8 kV Contact See Figures 3 and 4 V
Clamping Voltage TLP
(Note 2)
See Figures 9 through 12
V
C
I
PP
= 8 A
I
PP
= −8 A
IEC 61000−4−2 Level 2 equivalent
(±4 kV Contact, ±4 kV Air)
9.2
−4.5
V
I
PP
= 16 A
I
PP
= −16 A
IEC 61000−4−2 Level 4 equivalent
(±8 kV Contact, ±15 kV Air)
12.0
−8.0
Dynamic Resistance R
DYN
I/O Pin to GND
GND to I/O Pin
0.33
0.45
W
Junction Capacitance C
J
V
R
= 0 V, f = 1 MHz between I/O Pins and GND 0.30 0.35 pF
1. For test procedure see Figures 7 and 8 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z
0
= 50 W, t
p
= 100 ns, t
r
= 4 ns, averaging window; t
1
= 30 ns to t
2
= 60 ns.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

TPD2EUSB30DRTR

Mfr. #:
Manufacturer:
Texas Instruments
Description:
TVS Diodes / ESD Suppressors 2Ch ESD Solution
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet