LPC2103FBD48,118 Datasheet LPC2103FBD48,151, LPC2103FBD48,118, LPC2102FBD48,151 | P7-P9

Product data sheet Rev. 04 — 2 June 2009 7 of 37

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

P0.11/CTS1/

CAP1.1/AD0.4

[3]

I/O P0.11 — General purpose input/output digital pin.

I CTS1 — Clear to Send input for UART1.

I CAP1.1 — Capture input for Timer 1, channel 1.

I AD0.4 — ADC 0, input 4.

P0.12/DSR1/

MAT1.0/AD0.5

[3]

I/O P0.12 — General purpose input/output digital pin.

I DSR1 — Data Set Ready input for UART1.

O MAT1.0 — PWM output for Timer 1, channel 0.

I AD0.5 — ADC 0, input 5.

P0.13/DTR1/

MAT1.1

[1]

I/O P0.13 — General purpose input/output digital pin.

O DTR1 — Data Terminal Ready output for UART1.

O MAT1.1 — PWM output for Timer 1, channel 1.

P0.14/DCD1/

SCK1/EINT1

[4][5]

I/O P0.14 — General purpose input/output digital pin.

I DCD1 — Data Carrier Detect input for UART1.

I/O SCK1 — Serial Clock for SPI1. SPI clock output from master or input to slave.

I EINT1 — External interrupt 1 input.

P0.15/RI1/

EINT2

[4]

I/O P0.15 — General purpose input/output digital pin.

I RI1 — Ring Indicator input for UART1.

I EINT2 — External interrupt 2 input.

P0.16/EINT0/

MAT0.2

[4]

I/O P0.16 — General purpose input/output digital pin.

I EINT0 — External interrupt 0 input.

O MAT0.2 — PWM output for Timer 0, channel 2.

P0.17/CAP1.2/

SCL1

[6]

I/O P0.17 — General purpose input/output digital pin. The output is not

open-drain.

I CAP1.2 — Capture input for Timer 1, channel 2.

I/O SCL1 — I

C1 clock Input/output. This pin is an open-drain output if I

function is selected in the pin connect block.

P0.18/CAP1.3/

SDA1

[6]

I/O P0.18 — General purpose input/output digital pin. The output is not

open-drain.

I CAP1.3 — Capture input for Timer 1, channel 3.

I/O SDA1 — I

C1 data Input/output. This pin is an open-drain output if I

function is selected in the pin connect block.

P0.19/MAT1.2/

MISO1

[1]

I/O P0.19 — General purpose input/output digital pin.

O MAT1.2 — PWM output for Timer 1, channel 2.

I/O MISO1 — Master In Slave Out for SSP. Data input to SSP master or data

output from SSP slave.

P0.20/MAT1.3/

MOSI1

[1]

I/O P0.20 — General purpose input/output digital pin.

O MAT1.3 — PWM output for Timer 1, channel 3.

I/O MOSI1 — Master Out Slave for SSP. Data output from SSP master or data

input to SSP slave.

P0.21/SSEL1/

MAT3.0

[1]

I/O P0.21 — General purpose input/output digital pin.

I SSEL1 — Slave Select for SPI1. Selects the SPI interface as a slave.

O MAT3.0 — PWM output for Timer 3, channel 0.

Table 3. Pin description

…continued

Symbol Pin Type Description

Product data sheet Rev. 04 — 2 June 2009 8 of 37

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

P0.22/AD0.0 32

[3]

I/O P0.22 — General purpose input/output digital pin.

I AD0.0 — ADC 0, input 0.

P0.23/AD0.1 33

[3]

I/O P0.23 — General purpose input/output digital pin.

I AD0.1 — ADC 0, input 1.

P0.24/AD0.2 34

[3]

I/O P0.24 — General purpose input/output digital pin.

I AD0.2 — ADC 0, input 2.

P0.25/AD0.6 38

[3]

I/O P0.25 — General purpose input/output digital pin.

I AD0.6 — ADC 0, input 6.

P0.26/AD0.7 39

[3]

I/O P0.26 — General purpose input/output digital pin.

I AD0.7 — ADC 0, input 7.

P0.27/

TRST/

CAP2.0

[1]

I/O P0.27 — General purpose input/output digital pin.

TRST — Test Reset for JTAG interface. If DBGSEL is HIGH, this pin is

automatically conﬁgured for use with EmbeddedICE (Debug mode).

I CAP2.0 — Capture input for Timer 2, channel 0.

P0.28/TMS/

CAP2.1

[1]

I/O P0.28 — General purpose input/output digital pin.

I TMS — Test Mode Select for JTAG interface. If DBGSEL is HIGH, this pin is

automatically conﬁgured for use with EmbeddedICE (Debug mode).

I CAP2.1 — Capture input for Timer 2, channel 1.

P0.29/TCK/

CAP2.2

[1]

I/O P0.29 — General purpose input/output digital pin.

I TCK — Test Clock for JTAG interface. This clock must be slower than

⁄

of the

CPU clock (CCLK) for the JTAG interface to operate. If DBGSEL is HIGH, this

pin is automatically conﬁgured for use with EmbeddedICE (Debug mode).

I CAP2.2 — Capture input for Timer 2, channel 2.

P0.30/TDI/

MAT3.3

[1]

I/O P0.30 — General purpose input/output digital pin.

I TDI — Test Data In for JTAG interface. If DBGSEL is HIGH, this pin is

automatically conﬁgured for use with EmbeddedICE (Debug mode).

O MAT3.3 — PWM output 3 for Timer 3.

P0.31/TDO 16

[1]

O P0.31 — General purpose output only digital pin.

O TDO — Test Data Out for JTAG interface. If DBGSEL is HIGH, this pin is

automatically conﬁgured for use with EmbeddedICE (Debug mode).

RTCX1 20

[7][8]

I Input to the RTC oscillator circuit. Input voltage must not exceed 1.8 V.

RTCX2 25

[7][8]

O Output from the RTC oscillator circuit.

RTCK 26

[7]

I/O Returned test clock output: Extra signal added to the JTAG port. Assists

debugger synchronization when processor frequency varies. Bidirectional pin

with internal pull-up.

XTAL1 11 I Input to the oscillator circuit and internal clock generator circuits. Input voltage

must not exceed 1.8 V.

XTAL2 12 O Output from the oscillator ampliﬁer.

DBGSEL 27 I Debug select: When LOW, the part operates normally. When externally

pulled HIGH at reset, P0.27 to P0.31 are conﬁgured as JTAG port, and the

part is in Debug mode

[9]

. Input with internal pull-down.

RST 6 I External reset input: A LOW on this pin resets the device, causing I/O ports

and peripherals to take on their default states and processor execution to

begin at address 0. TTL with hysteresis, 5 V tolerant.

Table 3. Pin description

…continued

Symbol Pin Type Description

Product data sheet Rev. 04 — 2 June 2009 9 of 37

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

[1] 5 V tolerant (if V

DD(3V3)

and V

DDA

≥ 3.0 V) pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

[2] Open-drain 5 V tolerant (if V

DD(3V3)

and V

DDA

≥ 3.0 V) digital I/O I

C-bus 400 kHz speciﬁcation compatible pad. It requires external

pull-up to provide an output functionality. Open-drain conﬁguration applies to ALL functions on that pin.

[3] 5 V tolerant (if V

DD(3V3)

and V

DDA

≥ 3.0 V) pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and

analog input function. If conﬁgured for an input function, this pad utilizes built-in glitch ﬁlter that blocks pulses shorter than 3 ns. When

conﬁgured as an ADC input, digital section of the pad is disabled.

[4] 5 V tolerant (if V

DD(3V3)

and V

DDA

≥ 3.0 V) pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

If conﬁgured for an input function, this pad utilizes built-in glitch ﬁlter that blocks pulses shorter than 3 ns.

[5] A LOW level during reset on pin P0.14 is considered as an external hardware request to start the ISP command handler.

[6] Open-drain 5 V tolerant (if V

DD(3V3)

and V

DDA

≥ 3.0 V) digital I/O I

C-bus 400 kHz speciﬁcation compatible pad. It requires external

pull-up to provide an output functionality. Open-drain conﬁguration applies only to I

C function on that pin.

[7] Pad provides special analog functionality.

[8] For lowest power consumption, pin should be left ﬂoating when the RTC is not used.

[9] See

LPC2101/02/03 User manual UM10161

for details.

7, 19, 43 I Ground: 0 V reference.

SSA

31 I Analog ground: 0 V reference. This should be nominally the same voltage as

but should be isolated to minimize noise and error.

DDA

42 I Analog 3.3 V power supply: This should be nominally the same voltage as

DD(3V3)

but should be isolated to minimize noise and error. The level on this

pin also provides a voltage reference level for the ADC.

DD(1V8)

5I1.8 V core power supply: This is the power supply voltage for internal

circuitry and the on-chip PLL.

DD(3V3)

17, 40 I 3.3 V pad power supply: This is the power supply voltage for the I/O ports.

VBAT 4 I RTC power supply: 3.3 V on this pin supplies the power to the RTC.

Table 3. Pin description

…continued

Symbol Pin Type Description

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P37

LPC2103FBD48,118

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NXP Semiconductors

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ARM Microcontrollers - MCU 32K FL/8K RAM/8CH

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LPC2103FBD48,118

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