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8S89831AKILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
16©2017 Integrated Device Technology, Inc. November 9, 2017
8S89831I Datasheet
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
The LVPECL output driver circuit and termination are shown in Figure 8.
Figure 8. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
V
CC
– 2V.
• For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
– 0.85V
(V
CC_MAX
– V
OH_MAX
) = 0.85V
• For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
– 1.575V
(V
CC_MAX
– V
OL_MAX
) = 1.575V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OH_MAX
) = [(2V – (V
CC_MAX
– V
OH_MAX
))/R
L
] * (V
CC_MAX
– V
OH_MAX
) =
[(2V – 0.85V)/50] * 0.85V = 19.55mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OL_MAX
) = [(2V – (V
CC_MAX
– V
OL_MAX
))/R
L]
* (V
CC_MAX
– V
OL_MAX
) =
[(2V – 1.575V)/50] * 1.575V = 13.39mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.94mW
Transistor Count
The transistor count for 8S89831I is: 328
This device is pin and function compatible and a suggested replacement for 889831.
V
OUT
V
CC
V
CC
- 2V
Q1
RL
50Ω
17©2017 Integrated Device Technology, Inc. November 9, 2017
8S89831I Datasheet
Case Temperature Considerations
This device supports applications in a natural convection environment that does not have any thermal conductivity through ambient air. The
printed circuit board (PCB) is typically in a sealed enclosure without any natural or forced air flow and is kept at or below a specific temperature.
The device package design incorporates an exposed pad (ePad) with enhanced thermal parameters, which is soldered to the PCB where most
of the heat escapes from the bottom exposed pad. For this type of application, IDT recommends using the junction-to-board thermal
characterization parameter
JB
(Psi-JB) to calculate the junction temperature (T
J
) and ensure it does not exceed the maximum allowed
operating junction temperature in the Absolute Maximum Ratings.
The junction-to-board thermal characterization parameter,
JB,
is calculated using the following equation:
T
J
= T
B
+
JB
x P
D,
where:
• T
J
= Junction temperature at steady state condition in (
o
C)
• T
B
= Board or case temperature (Bottom) at steady state condition in (
o
C)
•
JB
=
Thermal characterization parameter to report the difference between junction temperature and the temperature of the board measured
at the top surface of the board
• P
D
= Power dissipation (W) in desired operating configuration
The ePad provides a low thermal resistance path for heat transfer to the PCB and represents the key pathway to transfer heat away from the
IC to the PCB. It is critical that the connection of the exposed pad to the PCB is properly constructed to maintain the desired IC bottom case
temperature (T
CB
). A good connection ensures that temperature at the exposed pad (T
CB
) and the board temperature (T
B
) are relatively the
same. An improper connection can lead to increased junction temperature, increased power consumption, and decreased electrical
performance. In addition, there could be long-term reliability issues and increased failure rate.
For the variables above, the junction temperature is equal to 106.2
o
C. Since this operating junction temperature is below the maximum
operating junction temperature of 125
o
C, there are no long term reliability concerns. In addition, since the junction temperature at which the
device was characterized using forced convection is 107.9
o
C, this device can function without the degradation of the specified AC or DC
parameters.
Example Calculation for Junction Temperature (T
J
): T
J
= T
B
+
JB
x P
D
Package type 16L-QFN
Body size (mm) 3.0
3.0 1.0 mm
ePad size (mm) 1.7
1.7 mm
Thermal Via 2
2 Matrix
JB
5.7
o
C/W
T
B
105
o
C
P
D
0.305W
T
J
T
B
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without
notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed
in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any
particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intel-
lectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved.
Tech Support
www.idt.com/go/support
Sales
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
8S89831I Datasheet
18©2017 Integrated Device Technology, Inc. November 9, 2017
Package Outline Drawings
The package outline drawings are located at the end of this document. The package information is the most current data available and is subject
to change without notice or revision of this document.
Ordering Information
Table 9. Ordering Information
Revision History
Part/Order Number Marking Package Shipping Packaging Temperature
8S89831AKILF 831A “Lead-Free” 16 Lead VFQFN Tube -40C to 85C
8S89831AKILFT 831A “Lead-Free” 16 Lead VFQFN Tape & Reel -40C to 85C
Revision Date Description of Change
November 9, 2017
Replaced operating temperature with junction temperature in Absolute Maximum Ratings; also removed the
package thermal information
Changed the T
A
and T
B
temperature ranges to indicate “or” in all electrical table titles
October 3, 2017
Added a new bullet to Features about board temperature
Added “TB = -40°C to 105°C” to Tables 4A, 4B, 4C, 4D, and 5
Added Case Temperature Considerations
September 22, 2017
Updated the package outline drawings; however, no mechanical changes
Completed other minor improvements
June 22, 2017
Updated the thermal characteristics in Table 6
Updated the package drawings - no technical changes
January 27, 2016
Removed ICS from part numbers where needed.
General Description - Deleted ICS chip.
Ordering Information - Deleted quantity in tape in reel. Deleted LF note below table.
Updated header and footer.
April 22, 2010
Deleted Differential Input with Built-in 50
Termination Unused Input Handling application section. This section
does not apply when there is only one input.
Power Considerations - in Power Dissipation section, corrected Power (RT) calculation. Calculation = 18mW
from 98mW. Total Power and Junction Temperature calculations have also been updated.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

8S89831AKILF

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Description:
Clock Buffer 1:4 Differential to LVEPCL/ECO Fanout Bu
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