11
LT1641-1/LT1641-2
164112fc
APPLICATIO S I FOR ATIO
WUU
U
V
CC
TIMER
SENSE GATE
876
54
21
3
D1
CMPZ
5248B
GND
PWRGD
FB
R5
10Ω
5%
ON
R1
294k
1%
V
IN
48V
UV = 37V
GND
1641-1 F12
R2
10.2k
1%
C2
0.68µF
R6,
1k, 5%
R
S
0.01Ω
C1
10nF
R3
143k
1%
R4
4.22k
1%
R7
47k
5%
+
C
L
220µF
Q2
MMBT5551LT1
V
OUT
LT1641-1
ACTIVE LOW
ENABLE MODULE
V
OUT
–
V
OUT
+
V
IN
–
ON/OFF
V
IN
+
Q1
IRF530
SHORT
PIN
Figure 12. Active Low Enable Module
R1
SENSE
RESISTOR, R
S
1641-1 F14
R2
V
CC
SENSE
ON
GND
LT1641-1
I
LOAD
I
LOAD
Figure 14. Recommended Layout for R1, R2 and R
S
Figure 13. Gate Drive vs Supply Voltage
V
CC
(V)
8
V
GATE
– V
CC
(V)
18
16
14
12
10
8
6
4
2
0
1641-1 F13
13 18 23
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
is recommended. The minimum trace width for 1oz cop-
per foil is 0.02" per amp to make sure the trace stays at a
reasonable temperature. 0.03" per amp or wider is recom-
mended. Note that 1oz copper exhibits a sheet resistance
of about 530µΩ/ . Small resistances add up quickly in
high current applications. To improve noise immunity, put
the resistor divider to the ON pin close to the chip and keep
traces to V
CC
and GND short. A 0.1µF capacitor from the
ON pin to GND also helps reject induced noise. Figure 14
shows a layout that addresses these issues.
