LT1641-2IS8#PBF Datasheet LT1641-2IS8#TRPBF, LT1641-1IS8#TRPBF, LT1641-2CS8#PBF | P7-P9

LT1641-1/LT1641-2

164112fc

1641-1 F02

GATE

PLHON

1.313V

PHLON

1.233V

1641-1 F03

PWRGD

PLHFB

1.313V

PHLFB

1.233V

– SENSE

1641-1 F04

GATE

PHLSENSE

47mV

TI I G DIAGRA S

WUW

Figure 2. ON to GATE Timing

Figure 3. FB to PWRGD Timing

Figure 4. SENSE to GATE Timing

APPLICATIO S I FOR ATIO

WUU

Hot Circuit Insertion

When circuit boards are inserted into a live backplane, the

supply bypass capacitors on the boards draw high peak

currents from the backplane power bus as they charge up.

The transient currents can permanently damage the con-

nector pins and glitch the system supply, causing other

boards in the system to reset.

The chip is designed to turn on a board’s supply voltage in

a controlled manner, allowing the board to be safely

inserted or removed from a live backplane. The chip also

provides undervoltage and overcurrent protection while a

power good output signal indicates when the output

supply voltage is ready.

Power-Up Sequence

The power supply on a board is controlled by placing an

external N-channel pass transistor (Q1) in the power path

(Figure 5). Resistor R

provides current detection and

capacitor C1 provides control of the GATE slew rate.

Resistor R6 provides current control loop compensation

while R5 prevents high frequency oscillations in Q1.

Resistors R1 and R2 provide undervoltage sensing.

After the power pins first make contact, transistor Q1 is

turned off. If the voltage at the ON pin exceeds the turn-on

threshold voltage, the voltage on the V

pin exceeds the

undervoltage lockout threshold, and the voltage on the

TIMER pin is less than 1.233V, transistor Q1 will be turned

on (Figure 6). The voltage at the GATE pin rises with a slope

equal to 10µA/C1 and the supply inrush current is set at

INRUSH

= C

• 10µA/C1. If the voltage across the current

sense resistor R

gets too high, the inrush current will then

be limited by the internal current limit circuitry which

adjusts the voltage on the GATE pin to maintain a constant

voltage across the sense resistor.

Once the voltage at the output has reached its final value,

as sensed by resistors R3 and R4, the PWRGD pin goes

high.

LT1641-1/LT1641-2

164112fc

Short-Circuit Protection

The chip features a programmable foldback current limit

with an electronic circuit breaker that protects against

short-circuits or excessive supply currents. The current

limit is set by placing a sense resistor between V

(Pin 8)

and SENSE (Pin 7).

To prevent excessive power dissipation in the pass tran-

sistor and to prevent voltage spikes on the input supply

during short-circuit conditions at the output, the current

folds back as a function of the output voltage, which is

sensed at the FB pin (Figure 7).

When the voltage at the FB pin is 0V, the current limit

circuit drives the GATE pin to force a constant 12mV drop

across the sense resistor. As the output voltage at the FB

pin increases, the voltage across the sense resistor in-

creases until the FB pin reaches 0.5V, at which point the

voltage across the sense resistor is held constant at 47mV.

The maximum current limit is calculated as:

LIMIT

= 47mV/R

SENSE

For a 0.025Ω sense resistor, the current limit is set at

1.88A and folds back to 480mA when the output is shorted

to ground.

The IC also features a variable overcurrent response time.

The time required to regulate Q1’s drain current depends

on: Q1’s input capacitance; gate capacitor C1 and com-

pensation resistor R6; and the internal delay from the

SENSE to the GATE pin. Figure 8 shows the delay from a

voltage step at the SENSE pin until the GATE voltage starts

falling, as a function of overdrive.

TIMER

The TIMER pin (Pin 5) provides a method for program-

ming the maximum time the chip is allowed to operate in

current limit. When the current limit circuitry is not active,

the TIMER pin is pulled to GND by a 3µA current source.

After the current limit circuit becomes active, an 80µA pull-

up current source is connected to the TIMER pin and the

voltage will rise with a slope equal to 77µA/C

TIMER

as long

as the current limit circuit remains active. Once the desired

maximum current limit time is set, the capacitor value is:

C(nF) = 62 • t(ms).

If the current limit circuit turns off, the TIMER pin will be

discharged to GND by the 3µA current source.

Whenever the TIMER pin reaches 1.233V, either the inter-

nal fault latch is set (LT1641-1) or the autorestart latch is

set (LT1641-2). The GATE pin is immediately pulled to

GND and the TIMER pin is pulled back to GND by the 3µA

APPLICATIO S I FOR ATIO

WUU

SHORT

TIMER

SENSE GATE

876

CMPZ

5248B

GND

PWRGD

10Ω

49.9k

24V

GND

1641-1 F05

3.4k

0.68µF

R6,

1k, 5%

0.025Ω

10nF

59k

3.57k

24k

OUT

LT1641-1

IRF530

Figure 5. Typical Application Figure 6. Power-Up Waveforms

LT1641-1/LT1641-2

164112fc

APPLICATIO S I FOR ATIO

WUU

Figure 8. Response Time to Overcurrent

12mV

0V 0.5V V

1641-1 F07

47mV

– V

SENSE

Figure 7. Current Limit Sense Voltage vs Feedback Pin Voltage

50mV 100mV 150mV 200mV

1641-1 F08

12µs

10µs

8µs

6µs

4µs

2µs

PROPAGATION DELAY

– V

SENSE

current source. When the TIMER pin falls below 0.5V, the

GATE pin either turns on automatically (LT1641-2) or once

the ON pin is pulsed low to reset the internal fault latch

(LT1641-1).

The waveform in Figure 9 shows how the output latches off

following a short-circuit. The drop across the sense resis-

tor is held at 12mV as the timer ramps up. Since the output

did not rise bringing FB above 0.5V, the circuit latches off.

For Figure 9, C

= 100nF.

Undervoltage and Overvoltage Detection

The ON pin can be used to detect an undervoltage condi-

tion at the power supply input. The ON pin is internally

connected to an analog comparator with 80mV of hyster-

esis. If the ON pin falls below its threshold voltage (1.233V),

the GATE pin is pulled low and is held low until ON is high

again.

Figure 10 shows an overvoltage detection circuit. When

the input voltage exceeds the Zener diode’s breakdown

voltage, D2 turns on and starts to pull the TIMER pin high.

After the TIMER pin is pulled higher than 1.233V, the fault

latch is set and the GATE pin is pulled to GND immediately,

turning off transistor Q1. The waveforms are shown in

Figure 11. Operation is restored either by interrupting

power or by pulsing ON low.

Power Good Detection

The chip includes a comparator for monitoring the output

voltage. The noninverting input (FB pin) is compared

against an internal 1.233V precision reference and exhib-

its 80mV hysteresis. The comparator’s output (PWRGD

pin) is an open collector capable of operating from a pull-

up as high as 100V.

The PWRGD pin can be used to directly enable/disable a

power module with an active high enable input. Figure 12

shows how to use the PWRGD pin to control an active low

enable input power module. Signal inversion is accom-

plished by transistor Q2 and R7.

Supply Transient Protection

The IC is 100% tested and guaranteed to be safe from

damage with supply voltages up to 100V. However, spikes

above 100V may damage the part. During a short-circuit

condition, the large change in currents flowing through

the power supply traces can cause inductive voltage

spikes which could exceed 100V. To minimize the spikes,

the power trace parasitic inductance should be minimized

by using wider traces or heavier trace plating and a 0.1µF

bypass capacitor placed between V

and GND. A surge

suppressor at the input can also prevent damage from

voltage surges.

P1-P3 P4-P6 P7-P9 P10-P12

LT1641-2IS8#PBF

Mfr. #:

Buy LT1641-2IS8#PBF

Manufacturer:

Analog Devices Inc.

Description:

Hot Swap Voltage Controllers Hot Swap Contr. +48V Auto-Retry

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LT1641-2IS8#PBF

LT1641-2IS8#PBF

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