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ADUM5201CRWZ-RL

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Data Sheet ADuM5200/ADuM5201/ADuM5202
Rev. B | Page 19 of 28
APPLICATIONS INFORMATION
The dc-to-dc converter section of the ADuM5200/ADuM5201/
ADuM5202 works on principles that are common to most
switching power supplies. It has a secondary side controller
architecture with isolated pulse-width modulation (PWM)
feedback. V
DD1
power is supplied to an oscillating circuit that
switches current into a chip scale air core transformer. Power
transferred to the secondary side is rectified and regulated to
either 3.3 V or 5 V. The secondary (V
ISO
) side controller regulates
the output by creating a PWM control signal that is sent to the
primary (V
DD1
) side by a dedicated iCoupler data channel. The
PWM modulates the oscillator circuit to control the power being
sent to the secondary side. Feedback allows for significantly
higher power and efficiency.
The ADuM5200/ADuM5201/ADuM5202 implements under-
voltage lockout (UVLO) with hysteresis on the V
DD1
power input.
This feature ensures that the converter does not enter oscillation
due to noisy input power or slow power-on ramp rates.
The ADuM5200/ADuM5201/ADuM5202 can accept an external
regulation control signal (RC
IN
) that can be connected to other
isoPower devices. This allows a single regulator to control multiple
power modules without contention. When accepting control from
a master power module, the V
ISO
pins can be connected together,
adding their power. Because there is only one feedback control
path, the supplies work together seamlessly. The ADuM5200/
ADuM5201/ADuM5202 can only regulate themselves or accept
regulation (as slave devices) from another device in this product
line; they cannot provide a regulation signal to other devices.
PCB LAYOUT
The ADuM5200/ADuM5201/ADuM5202 digital isolators
with 0.5 W isoPower, integrated dc-to-dc converter require no
external interface circuitry for the logic interfaces. Power supply
bypassing is required at the input and output supply pins (see
Figure 23). Note that low ESR bypass capacitors are required
between Pin 1 and Pin 2 and between Pin 15 and Pin 16, as
close to the chip pads as possible.
The power supply section of the ADuM5200/ADuM5201/
ADuM5202 uses a 180 MHz oscillator frequency to pass power
efficiently through its chip scale transformers. In addition, the
normal operation of the data section of the iCoupler introduces
switching transients on the power supply pins. Bypass capacitors
are required for several operating frequencies. Noise suppression
requires a low inductance, high frequency capacitor, whereas ripple
suppression and proper regulation require a large value capacitor.
These capacitors are most conveniently connected between
Pin 1 and Pin 2 for V
DD1
and between Pin 15 and Pin 16 for V
ISO
.
To suppress noise and reduce ripple, a parallel combination of
at least two capacitors is required. The recommended capacitor
values are 0.1 μF and 10 μF for V
DD1
. The smaller capacitor must
have a low ESR; for example, use of a ceramic capacitor is advised.
Note that the total lead length between the ends of the low ESR
capacitor and the input power supply pin must not exceed 2 mm.
Installing the bypass capacitor with traces more than 2 mm in
length may result in data corruption. Consider bypassing between
Pin 1 and Pin 8 and between Pin 9 and Pin 16 unless both common
ground pins are connected together close to the package.
V
DD1
BYPASS < 2mm
GND
1
V
IA
/V
OA
V
IB
/V
OB
V
ISO
GND
ISO
V
OA
/V
IA
V
OB
/V
IB
NC
V
SEL
RC
IN
RC
SEL
V
E1
/NC V
E2
/NC
GND
1
GND
ISO
07540-020
Figure 23. Recommended PCB Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling
that does occur affects all pins equally on a given component
side. Failure to ensure this can cause voltage differentials between
pins exceeding the absolute maximum ratings for the device
(specified in Table 19), thereby leading to latch-up and/or
permanent damage.
The ADuM5200/ADuM5201/ADuM5202 is a power device that
dissipates approximately 1 W of power when fully loaded and
running at maximum speed. Because it is not possible to apply a
heat sink to an isolation device, the device primarily depends
on heat dissipation into the PCB through the GND pins. If the
device is used at high ambient temperatures, provide a thermal
path from the GND pins to the PCB ground plane. The board
layout in Figure 23 shows enlarged pads for Pin 2, Pin 8, Pin 9,
and Pin 15. Multiple vias should be implemented from the pad
to the ground plane to significantly reduce the temperature
inside the chip. The dimensions of the expanded pads are at the
discretion of the designer and depend on the available board space.
START-UP BEHAVIOR
The ADuM5200/ADuM5201/ADuM5202 do not contain a soft
start circuit. Take the start-up current and voltage behavior into
account when designing with this device.
When power is applied to V
DD1
, the input switching circuit begins
to operate and draw current when the UVLO minimum voltage
is reached. The switching circuit drives the maximum available
power to the output until it reaches the regulation voltage where
PWM control begins. The amount of current and time this
takes depends on the load and the V
DD1
slew rate.
With a fast V
DD1
slew rate (200 μs or less), the peak current
draws up to 100 mA/V of V
DD1
. The input voltage goes high
faster than the output can turn on; therefore, the peak current
is proportional to the maximum input voltage.
ADuM5200/ADuM5201/ADuM5202 Data Sheet
Rev. B | Page 20 of 28
With a slow V
DD1
slew rate (in the millisecond range), the input
voltage is not changing quickly when V
DD1
reaches the UVLO
minimum voltage. The current surge is approximately 300 mA
because V
DD1
is nearly constant at the 2.7 V UVLO voltage. The
behavior during startup is similar to when the device load is a
short circuit; these values are consistent with the short-circuit
current shown in Figure 12.
When starting the device for V
ISO
= 5 V operation, do not limit
the current available to the V
DD1
power pin to less than 300 mA.
The ADuM5200/ADuM5201/ADuM5202 devices may not be able
to drive the output to the regulation point if a current-limiting
device clamps the V
DD1
voltage during startup. As a result, the
ADuM5200/ADuM5201/ADuM5202 devices can draw large
amounts of current at low voltage for extended periods of time.
The output voltage of the ADuM5200/ADuM5201/ADuM5202
exhibits V
ISO
overshoot during startup. If this could potentially
damage components attached to V
ISO
, then a voltage-limiting
device, such as a Zener diode, can be used to clamp the voltage.
Typical behavior is shown in Figure 17 and Figure 18.
EMI CONSIDERATIONS
The dc-to-dc converter section of the ADuM5200/ADuM5201/
ADuM5202 devices must operate at 180 MHz to allow efficient
power transfer through the small transformers. This creates
high frequency currents that can propagate in circuit board
ground and power planes, causing edge emissions and dipole
radiation between the primary and secondary ground planes.
Grounded enclosures are recommended for applications that use
these devices. If grounded enclosures are not possible, follow
good RF design practices in the layout of the PCB. See the
AN-0971 Application Note for board layout recommendations.
PROPAGATION DELAY PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output may differ from the propagation delay
to a logic high.
INPUT (
V
IX
)
OUTPUT (V
OX
)
t
PLH
t
PHL
50%
50%
07540-118
Figure 24. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of
how accurately timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM5200/ADuM5201/ADuM5202 component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM5200/
ADuM5201/ADuM5202 components operating under the
same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
the pulses, indicating input logic transitions. In the absence of
logic transitions at the input for more than 1 μs, a periodic set
of refresh pulses indicative of the correct input state are sent to
ensure dc correctness at the output. If the decoder receives no
internal pulses of more than about 5 μs, the input side is assumed
to be unpowered or nonfunctional, in which case the isolator
output is forced to a default state (see Table 24) by the watchdog
timer circuit.
The limitation on the magnetic field immunity of the ADuM5200/
ADuM5201/ADuM5202 is set by the condition in which induced
voltage in the receiving coil of the transformer is sufficiently
large to either falsely set or reset the decoder. The following analysis
defines the conditions under which this may occur. The 3 V
operating condition of the ADuM5200/ADuM5201/ADuM5202
is examined because it represents the most susceptible mode of
operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = (−dβ/dt)∑πr
n
2
; n = 1, 2, … , N
where:
β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.
r
n
is the radius of the n
th
turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM5200/
ADuM5201/ADuM5202 and an imposed requirement that the
induced voltage be, at most, 50% of the 0.5 V margin at the
decoder, a maximum allowable magnetic field is calculated as
shown in Figure 25.
MAGNETIC FIELD FREQUENCY (Hz)
100
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
0.001
1M
10
0.01
1k 10k 10M
0.1
1
100M100k
07540-119
Figure 25. Maximum Allowable External Magnetic Flux Density
Data Sheet ADuM5200/ADuM5201/ADuM5202
Rev. B | Page 21 of 28
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse
(and is of the worst-case polarity), it reduces the received pulse
from >1.0 V to 0.75 V—still well above the 0.5 V sensing
threshold of the decoder.
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances from the ADuM5200/
ADuM5201/ADuM5202 transformers. Figure 26 expresses
these allowable current magnitudes as a function of frequency
for selected distances. As shown, the ADuM5200/ADuM5201/
ADuM5202 are extremely immune and can be affected only by
extremely large currents operated at high frequency very close
to the component. For the 1 MHz example noted, a 0.5 kA current
placed 5 mm away from the ADuM5200/ADuM5201/ADuM5202
is required to affect the operation of the component.
MAGNETIC FIELD FREQUENCY (Hz)
MAXIMUM ALLOWABLE CURRENT (kA)
1000
100
10
1
0.1
0.01
1k 10k 100M100k 1M 10M
DISTANCE = 5mm
DISTANCE = 1m
DISTANCE = 100mm
07540-120
Figure 26. Maximum Allowable Current for Various Current-to-
ADuM5200/ADuM5201/ADuM5202 Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by PCB traces can induce error
voltages sufficiently large enough to trigger the thresholds of
succeeding circuitry. Exercise care in the layout of such traces
to avoid this possibility.
POWER CONSUMPTION
The V
DD1
power supply input provides power to the iCoupler data
channels as well as to the power converter. For this reason, the
quiescent currents drawn by the data converter and the primary
and secondary input/output channels cannot be determined sepa-
rately. All of these quiescent power demands have been combined
into the I
DD1 (Q)
current shown in Figure 27. The total I
DD1
supply
current is the sum of the quiescent operating current, dynamic
current I
DD1 (D)
demanded by the I/O channels, and any external
I
ISO
load.
07540-021
CONVERTER
PRIMARY
I
DD1(Q)
I
ISO
I
DD1(D)
I
DDP(D)
I
ISO(D)
CONVERTER
SECONDARY
PRIMARY
DATA I/O
2-CHANNEL
SECONDARY
DATA I/O
2-CHANNEL
Figure 27. Power Consumption Within the ADuM5200/ADuM5201/ADuM5202
Both dynamic input and output current is consumed only when
operating at channel speeds higher than the rate of f
r
. Because
each channel has a dynamic current determined by its data rate,
Figure 19 shows the current for a channel in the forward direction,
which means that the input is on the primary side of the part.
Figure 20 shows the current for a channel in the reverse direction,
which means that the input is on the secondary side of the part.
Both figures assume a typical 15 pF load. The following
relationship allows the total I
DD1
current to be calculated:
I
DD1
= (I
ISO
× V
ISO
)/(E × V
DD1
) + ∑ I
CHn
; n = 1 to 4 (1)
where:
I
DD1
is the total supply input current.
I
CHn
is the current drawn by a single channel determined from
Figure 19 or Figure 20, depending on channel direction.
I
ISO
is the current drawn by the secondary side external loads.
E is the power supply efficiency at 100 mA load from Figure 9
at the V
ISO
and V
DD1
condition of interest.
Calculate the maximum external load by subtracting the dynamic
output load from the maximum allowable load.
I
ISO (LOAD)
= I
ISO (MAX)
− ∑ I
ISO (D)n
; n = 1 to 4 (2)
where:
I
ISO (LOAD)
is the current available to supply an external secondary
side load.
I
ISO (MAX)
is the maximum external secondary side load current
available at V
ISO
.
I
ISO (D)n
is the dynamic load current drawn from V
ISO
by an input
or output channel, as shown in Figure 19 and Figure 20. Data is
presented assuming a typical 15 pF load.
The preceding analysis assumes a 15 pF capacitive load on each
data output. If the capacitive load is larger than 15 pF, the addi-
tional current must be included in the analysis of I
DD1
and I
ISO (LOAD)
.
To deter mi ne I
DD1
in Equation 1, additional primary side
dynamic output current (I
AOD
) is added directly to I
DD1
.
Additional secondary side dynamic output current (I
AOD
) is
added to I
ISO
on a per-channel basis.
To deter mi ne I
ISO (LOAD)
in Equation 2, additional secondary
side output current (I
AOD
) is subtracted from I
ISO (MAX)
on a
per-channel basis.
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ADUM5201CRWZ-RL

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Digital Isolators Dual-CH w/ Intg DC/DC Converter
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