DS1318E+ Datasheet DS1318E+ | P10-P12

DS1318

Counter Operation

The binary time information is obtained by reading the

appropriate register bytes. Registers 02h through 05h

contain the time in seconds from an arbitrary reference

time determined by the user. Registers 00h and 01h

contain the fractional seconds count. A buffered copy

of the clock registers (A0–A5), updated every 244µs,

allows the user to read and write the registers while the

internal registers continue to increment. However, it is

possible to read or write inconsistent data, or for a write

to corrupt the current buffered read copy, if an update

occurs during the read or write. Several methods may

be used to ensure that the data is accurate.

The clock registers can be read, with the least-signifi-

cant byte (LSB) being read once at the beginning and

again after the other registers have been read (i.e.,

A2–A5, A2). If the LSB register data has changed, the

registers should be re-read until the LSB register data

matches. If the subseconds0 register is used, the user

never has more than 244µs to read all the registers

before a mismatch occurs. In addition, if the routine

used to read the registers takes approximately 1.95ms

to read the registers, it is possible that the

subseconds0 register could roll over to the same value

as previously read.

Other methods use the TE and UIP bits to synchronize

accessing the clock registers to ensure that the data are

valid. These methods are discussed in later sections.

Alarm

To use the alarm function, the user writes registers 06h

through 09h with a time in seconds. When the current

time in seconds becomes equal to the alarm value, the

ALMF bit in the status register (0Ch) is set to 1. If the

AIE bit in control register A is set to 1 by the user, then

the IRQ pin is driven low when the ALMF bit is set to 1.

The alarm and IRQ output operate when the device is

running from either supply.

Periodic Flag

Writing a non-zero value into the periodic flag rate-

select bits in control register B enables the periodic

flag operation. The periodic flag is set to logic 1 when

the internal counter reaches the selected value. Writing

the PF bit to 0 resets the periodic flag. If the flag is not

reset, it remains high. Once the PF bit is set, the inter-

nal counter continues counting, and attempts to set the

PF bit again when the count again matches the select-

ed rate value. Clearing the PF bit has no effect on the

internal counter. If the PIE bit in control register A is set

to 1, the IRQ output goes low when the PF bit is set.

The periodic flag and IRQ output operates when the

device is running from either supply.

Note that writing to the subseconds or seconds regis-

ters affects the setting of the PF flag and IRQ output.

The square-wave output uses a separate prescaler and

is not affected by changes to the subseconds or sec-

onds bits.

Parallel-Interface Elapsed Time Counter

10 ____________________________________________________________________

Table 3. Address Map

Note: Unless otherwise specified, the state of the registers is not defined when power is first applied.

ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION RANGE

00h SS3 SS2 SS1 SS0 0 0 0 SQWS Subseconds0 00–F0h

01h SS11 SS10 SS9 SS8 SS7 SS6 SS5 SS4 Subseconds1 00–FFh

02h S7 S6 S5 S4 S3 S2 S1 S0 Seconds0 00–FFh

03h S15 S14 S13 S12 S11 S10 S9 S8 Seconds1 00–FFh

04h S23 S22 S21 S20 S19 S18 S17 S16 Seconds2 00–FFh

05h S31 S30 S29 S28 S27 S26 S25 S24 Seconds3 00–FFh

06h ALM7 ALM6 ALM5 ALM4 ALM3 ALM2 ALM1 ALM0 Alarm0 00–FFh

07h ALM15 ALM14 ALM13 ALM12 ALM11 ALM10 ALM9 ALM8 Alarm1 00–FFh

08h ALM23 ALM22 ALM21 ALM20 ALM19 ALM18 ALM17 ALM16 Alarm2 00–FFh

09h ALM31 ALM30 ALM29 ALM28 ALM27 ALM26 ALM25 ALM24 Alarm3 00–FFh

0Ah TE ENOSC CCFG1 CCFG0 EPOL SQWE PIE AIE ControlA 00–FFh

0Bh PRS3 PRS2 PRS1 PRS0 SRS3 SRS2 SRS1 SRS0 ControlB 00–FFh

0Ch OSF UIP 0 0 0 0 PF ALMF Status —

Special-Purpose Registers

The DS1318 has three additional registers (control A,

control B, and status) that control the clock, alarms,

square wave, and interrupt output. The subseconds0

in the bit 0 location. Writing the SQWS bit to 1 clears

the square-wave prescaler and holds it in reset. Only

the frequencies below 4096Hz are reset. Writing the bit

back to 0 takes the prescaler out of reset and starts the

square wave running.

Bit 7: Transfer Enable (TE). When TE is set to logic 1,

the DS1318 continues to update the user copy of the

time value as it receives 4,096Hz clock pulses from the

oscillator. To ensure reading valid time data from the

part, the user should set TE to logic 0 before reading

registers 00–05h. TE must be enabled (logic 1) for at

least 244µs to ensure that a transfer occurs. Note that

because of the 244µs restriction, sequential values of

the subseconds0 register cannot be read when TE

is used.

It is possible that TE could be set to logic 0 while a

transfer is taking place. In that case, the buffered data

could be invalid. To prevent this, the UIP bit, described

later, should be used. To write data to the clock regis-

ters, the user should set TE to logic 0, write the regis-

ters, and set TE to logic 1.

Bit 6: Enable Oscillator (ENOSC). When ENOSC is set

to logic 1, the DS1318 crystal oscillator becomes

enabled. Actual startup time for the oscillator depends on

many external variables and is not a specified parameter.

Bits 5, 4: Clock Configuration 1, 0 (CCFG1, CCFG0).

These bits determine which of the four possible modes

the DS1318 uses to clock its timekeeping registers:

Bit 3: External Polarity (EPOL). This bit controls the

polarity on the EXT pin input when the CCFG1 and

CCFG0 bits are equal to 0 and 1, respectively. When

EPOL is set to logic 1, the registers count when the EXT

pin is 1. When EPOL is set to logic 0, the registers

count when the EXT pin is logic 0.

Bit 2: Square-Wave Enable (SQWE). When SQWE is

set to logic 1, a frequency determined by the SRSx bits

in control register B (0Bh) is output on the SQW pin.

When SQWE is logic 0, the SQW pin is always 0. When

the part is in power-fail, the SQW pin is always high-

impedance. The square-wave output uses a separate

prescaler from the one used by PF, IRQ, UIP, and the

up counter. The SQWS bit in control register A can be

used to synchronize the square-wave output to within

244µs of the other events.

Bit 1: Periodic Interrupt Enable (PIE). When PIE is set

to logic 1, the DS1318 sets the IRQ pin low whenever

the PF flag is set to 1. When PIE is 0, the PF flag does

not affect the IRQ pin.

Bit 0: Alarm Interrupt Enable (AIE). When AIE is set to

logic 1, the DS1318 sets the IRQ pin low whenever the

ALMF flag is set to 1. When AIE is 0, the ALMF flag

does not affect the IRQ pin.

DS1318

Parallel-Interface Elapsed Time Counter

____________________________________________________________________ 11

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

TE ENOSC CCFG1 CCFG0 EPOL SQWE PIE AIE

Control Register A (0Ah)

CCFG1 CCFG0 MODE

0 0 Always clocks the registers (normal mode)

Clocks when the EXT pin is “active” and

is greater than V

(event-timer mode,

depends on EPOL bit)

Clocks registers when part is running on

BAT

DS1318

Bits 7 to 4: Periodic Rate Select (PRS3–PRS0). When

the oscillator is enabled (ENOSC = 1) the PF flag is set

at the rates determined by the following table:

Bits 3 to 0: Square-Wave Rate Select (SRS3–SRS0).

When the oscillator is enabled (ENOSC = 1) and run-

ning, and the square-wave pin is enabled (SQWE = 1),

the SQW pin outputs a square-wave signal determined

by the SRS bits according to the following table:

Parallel-Interface Elapsed Time Counter

12 ____________________________________________________________________

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

PRS3 PRS2 PRS1 PRS0 SRS3 SRS2 SRS1 SRS0

Control Register B (0Bh)

PRS3 PRS2 PRS1 PRS0

PERIODIC FLAG

FREQUENCY

0 0 0 0 Periodic Flag Not Set

0 0 0 1 4096Hz

0 0 1 0 2048Hz

0 0 1 1 1024Hz

0 1 0 0 512Hz

0 1 0 1 256Hz

0 1 1 0 128Hz

0 1 1 1 8Hz

1 0 0 0 4Hz

1 0 0 1 2Hz

1 0 1 0 1Hz

10 1 1

1/64Hz

(Once per 1.067 Minutes)

11 0 0

1/4096Hz

(Once per 1.138 Hours)

11 0 1

1/65536Hz

(Once per 1.318 Days)

11 1 0

1/524288Hz

(Once per 0.8669 Weeks)

11 1 1

1/2097152Hz

(Once per 24.27 Days)

SRS3 SRS2 SRS1 SRS0

SQUARE-WAVE OUTPUT

FREQUENCY (Hz)

0 0 0 0 32,768

0 0 0 1 8192

0 0 1 0 4096

0 0 1 1 2048

0 1 0 0 1024

0 1 0 1 512

0 1 1 0 256

0 1 1 1 128

10 0 0 64

10 0 1 32

10 1 0 16

10 1 1 8

11 0 0 4

11 0 1 2

11 1 0 1

1 1 1 1 0.5

Periodic Flag Frequency When ENOSC = 1

Square-Wave Output Frequency When SQWE = 1,

ENOSC = 1

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

DS1318E+

Mfr. #:

Buy DS1318E+

Manufacturer:

Maxim Integrated

Description:

Real Time Clock Parallel-Interface Elapsed Time Cntr

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet

DS1318E+