LTC1407/LTC1407A
14
1407fb
APPLICATIONS INFORMATION
Integral nonlinearity errors (INL) and differential nonlinear-
ity errors (DNL) are largely independent of the common
mode voltage. However, the offset error will vary. CMRR
is typically better than 60dB.
Figure 4 shows the ideal input/output characteristics for
the LTC1407/LTC1407A. The code transitions occur mid-
way between successive integer LSB values (i.e., 0.5LSB,
1.5LSB, 2.5LSB, FS – 1.5LSB). The output code is natural
binary with 1LSB = 2.5V/16384 = 153µV for the LTC1407A
and 1LSB = 2.5V/4096 = 610µV for the LTC1407. The
LTC1407A has 1LSB RMS of Gaussian white noise.
Board Layout and Bypassing
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC1407/LTC1407A, a printed circuit
board with ground plane is required. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track. If optimum phase match between
the inputs is desired, the length of the four input wires of
the two input channels should be kept matched. But each
pair of input wires to the two input channels should be
kept separated by a ground trace to avoid high frequency
crosstalk between channels.
High quality tantalum and ceramic bypass capacitors
should be used at the V
DD
and V
REF
pins as shown in the
Block Diagram on the fi rst page of this data sheet. For
optimum performance, a 10µF surface mount tantalum
capacitor with a 0.1µF ceramic is recommended for the V
DD
and V
REF
pins. Alternatively, 10µF ceramic chip capacitors
such as X5R or X7R may be used. The capacitors must
be located as close to the pins as possible. The traces
connecting the pins and the bypass capacitors must be
kept short and should be made as wide as possible. The
V
DD
bypass capacitor returns to GND (Pin 6) and the
V
REF
bypass capacitor returns to the Exposed Pad ground
(Pin 11). Care should be taken to place the 0.1µF V
DD
bypass capacitor as close to Pins 6 and 7 as possible.
Figure 5 shows the recommended system ground connec-
tions. All analog circuitry grounds should be terminated at
the LTC1407/LTC1407A Exposed Pad. The ground return
from the LTC1407/LTC1407A Pin 6 to the power supply
should be low impedance for noise-free operation. The
Exposed Pad of the 10-lead MSE package is also tied to
Pin 6 and the LTC1407/LTC1407A GND. The Exposed Pad
should be soldered on the PC board to reduce ground
connection inductance. Digital circuitry grounds must be
connected to the digital supply common.
Figure 4. LTC1407/LTC1407A Transfer Characteristic
INPUT VOLTAGE (V)
UNIPOLAR OUTPUT CODE
1407 F04
111...111
111...110
111...101
000...000
000...001
000...010
FS – 1LSB0
