LTC1407/LTC1407A
5
1407fb
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground GND.
Note 3: When these pins are taken below GND or above V
DD
, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V
DD
without latchup.
Note 4: Offset and range specifi cations apply for a single-ended CH0
+
or CH1
+
input with CH0
–
or CH1
–
grounded and using the internal 2.5V reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
defi ned as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defi ned for the voltage difference
between CH0
+
and CH0
–
or CH1
+
and CH1
–
.
Note 9: The absolute voltage at CH0
+
,
CH0
–
, CH1
+
and CH1
–
must be
within this range.
Note 10: If less than 3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
32nd rising clock and it is ended by the rising edge of CONV.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10µF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5V
P-P
input sine wave.
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17: The LTC1407A is measured and specifi ed with 14-bit resolution
(1LSB = 152µV) and the LTC1407 is measured and specifi ed with 12-bit
resolution (1LSB = 610µV).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
7
32nd SCK↑ to CONV↑ Interval (Affects Acquisition Period)
(Notes 6, 7, 13) 45 ns
t
8
Minimum Delay from SCK to Valid Bits 0 Through 11 (Notes 6, 12) 8 ns
t
9
SCK to Hi-Z at SDO (Notes 6, 12) 6 ns
t
10
Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns
t
12
V
REF
Settling Time After Sleep-to-Wake Transition (Notes 6, 14) 2 ms
TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at T
A
= 25°C. V
DD
= 3V.
TYPICAL PERFORMANCE CHARACTERISTICS
ENOBs and SINAD
vs Input Sinewave Frequency
THD, 2nd and 3rd
vs Input Frequency SFDR vs Input Frequency
V
DD
= 3V, T
A
= 25°C (LTC1407A)
FREQUENCY (MHz)
0.1
10.0
ENOBs (BITS)
SINAD (dB)
11.0
12.0
1 10 100
1407 G01
9.0
9.5
10.5
11.5
8.5
8.0
62
68
74
56
59
65
71
53
50
FREQUENCY (MHz)
0.1
–80
THD, 2nd, 3rd (dB)
–74
–68
–62
–56
1 10 100
1407 G02
–86
–92
–98
–104
–50
–44
THD
3rd
2nd
FREQUENCY (MHz)
0.1
68
SFDR (dB)
56
44
1 10 100
1407 G19
80
74
62
50
86
92
98
104
