SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 26 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
7.3 Register descriptions
7.3.1 Mode registers
7.3.1.1 Mode Register 0 channel A (MR0A)
Table 21. ROPR - Reset Output Port bits Register (ROPR)
7 6 5 4 3 2 1 0
reset OP7 reset OP6 reset OP5 reset OP4 reset OP3 reset OP2 reset OP1 reset OP0
Table 22. OPCR - Output Port Configuration Register
OP1 and OP0 are the RTSN output and are controlled by the MR register
7 6 5 4 3 2 1 0
configure
OP7
configure
OP6
configure
OP5
configure
OP4
configure
OP3
configure
OP3
configure
OP2
configure
OP2
Table 23. MR0A - Mode Register 0 channel A (address 0x0) bit allocation
MR0 is accessed by setting the MR pointer to logic 0 via the command register command B.
7 6 5 4 3 2 1 0
RxWATCHDOG RxINT[2] TxINT[1:0] FIFOSIZE BAUDRATE
EXTENDED II
TEST2 BAUDRATE
EXTENDED I
Table 24. MR0A - Mode Register 0 channel A (address 0x0) bit description
Bit Symbol Description
7 RxWATCHDOG This bit controls the receiver watchdog timer.
0 = disable
1 = enable
When enabled, the watchdog timer will generate a receiver interrupt if
the receiver FIFO has not been accessed within 64 bit times of the
receiver 1× clock. The watchdog timer is used to alert the control
processor that data is in the Rx FIFO that has not been read. This
situation will occur when the byte count of the last part of a message
is not large enough to generate an interrupt.
The watchdog timer presents itself as a receiver interrupt with the
RxRDY bit set in SR and ISR.
6 RxINT[2] Bit 2 of receiver FIFO interrupt level. This bit along with bit 6 of MR1
sets the fill level of the FIFO that generates the receiver interrupt.
Note that this control is split between MR0 and MR1. This is for
backward compatibility to the SC26C92 and SCC2681.
For the receiver these bits control the number of FIFO positions filled
when the receiver will attempt to interrupt. After the reset the receiver
FIFO is empty. The default setting of these bits cause the receiver to
attempt to interrupt when it has one or more bytes in it; see
Table 25.
5 and 4 TxINT[1:0] Transmitter interrupt fill level. For the transmitter these bits control the
number of FIFO positions empty when the receiver will attempt to
interrupt; see
Table 26. After the reset the transmit FIFO has 8 bytes
empty. It will then attempt to interrupt as soon as the transmitter is
enabled. The default setting (TxINT[1:0] = 00) condition the
transmitter to attempt to interrupt only when it is completely empty. As
soon as one byte is loaded, it is no longer empty and hence will
withdraw its interrupt request.
