SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 52 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
(1) V
CC
= 3.3 V; T
amb
=25°C
(2) V
CC
= 5.0 V; T
amb
=25°C
Bus cycle times:
80xxx mode: t
DD
+t
RWD
= 70 ns for V
CC
= 5 V or 40 ns for V
CC
= 3.3 V + rise and fall time of control signals.
68xxx mode: t
CSC
+t
DAT
+ 1 cycle of the X1 clock for = 70 ns for V
CC
=5V+rise and fall time of control signals.
Fig 9. Port timing as a function of capacitive loading at typical conditions
C
L
(pF)
0 2401608040 200120
001aae302
20
40
60
t
DD
(ns)
0
30 pF12 pF 100 pF 125 pF
(2)
230 pF
(1)
SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 53 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
[1] The following conditions apply:
a) Parameters are valid over specified temperature and voltage range.
b) All voltage measurements are referenced to ground. For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of
5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8V
CC
. All time measurements are referenced at input voltages of 0.8 V
and 2.0 V, and output voltages of 0.8 V and 2.0 V, as appropriate.
c) Typical values are at 25 °C, typical supply voltages, and typical processing parameters.
[2] Test conditions for outputs: C
L
= 125 pF, except interrupt outputs. Test conditions for interrupt outputs: C
L
= 125 pF,
constant current source = 2.6 mA.
[3] Input port pins have active pull-up transistors that will source a typical 2 µA from V
CC
when they are at V
SS
. Input port pins at V
CC
source
0.0 µA.
[4] All outputs are disconnected. Inputs are switching between CMOS levels of V
CC
0.2 V and V
SS
+ 0.2 V.
Table 66. Static characteristics, 3.3 V operation
[1]
V
CC
= 3.3 V
±
10 %; T
amb
=
40
°
Cto+85
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V
IL
input LOW voltage - 0.65 0.2V
CC
V
V
IH
input HIGH voltage 0.8V
CC
1.7 - V
V
OL
output LOW voltage I
OL
= 2.4 mA - 0.2 0.4 V
V
OH
output HIGH voltage except open-drain outputs;
I
OH
= 400 µA
[2]
V
CC
0.5 V
CC
0.2 - V
I
I(1XPD)
Power-down mode input
current on pin X1/CLK
V
I
= 0 V to V
CC
0.5 +0.05 +0.5 µA
I
IL(X1)
operating input LOW current
on pin X1/CLK
V
I
=0V 80 - 0 µA
I
IH(X1)
operating input HIGH current
on pin X1/CLK
V
I
=V
CC
0- 80µA
I
I
input leakage current V
I
= 0 V to V
CC
all except input port pins
[3]
0.5 +0.05 +0.5 µA
input port pins
[3]
8 +0.5 +0.5 µA
I
OZH
output off current HIGH,
3-state data bus
V
I
=V
CC
- - 0.5 µA
I
OZL
output off current LOW, 3-state
data bus
V
I
=0V 0.5 - - µA
I
ODL
open-drain output LOW current
in off state
V
I
=0V 0.5 - - µA
I
ODH
open-drain output HIGH
current in off state
V
I
=V
CC
- - 0.5 µA
I
CC
power supply current CMOS input levels
[4]
operating mode - - 5 mA
Power-down mode - 1 5.0 µA
SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 54 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
10. Dynamic characteristics
Table 67. Dynamic characteristics, 5 V operation
[1]
V
CC
= 5.0 V
±
10 %, T
amb
=
40
°
C to +85
°
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Reset timing (see
Figure 10)
t
RES
reset pulse width 100 18 - ns
Bus timing
[2]
(see Figure 11)
t
AS
A0 to A3 set-up time to RDN, WRN LOW 10 6 - ns
t
AH
A0 to A3 hold time from RDN, WRN LOW 20 12 - ns
t
CS
CEN set-up time to RDN, WRN LOW 0 - - ns
t
CH
CEN hold time from RDN, WRN LOW 0 - - ns
t
RW
WRN, RDN pulse width (LOW time) 15 8 - ns
t
DD
data valid after RDN LOW 125 pF load; see Figure 9
for smaller loads
- 4055ns
t
DA
RDN LOW to data bus active
[3]
0--ns
t
DF
data bus floating after RDN or CEN HIGH - - 20 ns
t
DI
RDN or CEN HIGH to data bus invalid
[4]
0--ns
t
DS
data bus set-up time before WRN or CEN
HIGH (write cycle)
25 17 - ns
t
DH
data hold time after WRN HIGH 0 12 - ns
t
RWD
HIGH time between read and/or write
cycles
[2][4]
17 10 - ns
Port timing
[2]
(see Figure 15)
t
PS
port in set-up time before RDN LOW
(Read IP ports cycle)
0 20 - ns
t
PH
port in hold time after RDN HIGH 0 20 - ns
t
PD
OP port valid after WRN or CEN HIGH
(OPR write cycle)
- 4060ns
Interrupt timing (see
Figure 16)
t
IR
INTRN (or OP3 to OP7 when used as
interrupts)
read Rx FIFO
(RxRDY/FFULL interrupt)
- 4060ns
write Tx FIFO (TxRDY
interrupt)
- 4060ns
reset command (delta
break change interrupt)
- 4060ns
stop C/T command
(counter/timer interrupt
- 4060ns
read IPCR (delta input port
change interrupt)
- 4060ns
write IMR (clear of change
interrupt mask bit(s))
- 4060ns

SC28L92A1A,512

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 3V-5V 2CH UART INTEL/MOT INTRF
Lifecycle:
New from this manufacturer.
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