LT4351
16
4351fd
GATE OUTV
IN
UV
OV
1µF
10µF
MBR0530
MBR0530
R1
1.69k
1%
R
B
25.5k
1%
V
IN
5V
LT4351
SW
V
DD
STATUS
5
FAULT
GND
Si4838DY
3
7
6
4
2
1 10
9
8
R
A
1.47k
1%
R2
24.9k
1%
1Ω
0.1µF
220µF
10µF
5V
2k
4351 F15
OUT
2k
10µF
4.7µH
Figure 15. 5V/5A Design Example
Design Example
The following demonstrates the calculations involved for
setting design components for a 5V system that requires
5A. Two supplies are used to do this. The V
IN
supply will
be deemed in spec when it is within ±5% of nominal. Allow
5% of hysteresis for UV.
So,
UV
FAULT
= 4.75V, UV
HYST
= 0.25V
OV
FAULT
= 5.5
Two separate resistive dividers are used.
For the UV divider:
R2 =
UV
HYST
I
UVHYST
=
0.25V
10µA
= 25k Use 24.9k
( )
R1=
R2 • V
UV
UV
FAULT
– V
UV
=
24.9k • 0.3V
4.75V – 0.3V
R1 = 1.68k. The closest 1% value is 1.69k
The OV resistors are set as a straight resistive divider.
If the current in the R
A
, R
B
divider is 200µA, then:
R
A
=
0.3V
200mA
= 1.5k use 1.47k (1%)
then
R
B
=
OV
FAULT
V
OV
– 1
R
A
=
5.5
0.3
– 1
1.47k
R
B
= 25.48, use 25.5k
For regulation, the MOSFETs must have:
R
DS
<
15mV
2 • 5A
= 1.5mΩ
This very low value cannot be accomplished with a single
set of MOSFETs so a decision must be made whether to
use multiple MOSFETs or to live with an unregulated off-
set. Since low mΩ R
DS(ON)
is available, the IR drop using
a single MOSFET would still be acceptable. For R
DS(ON)
= 4mΩ the drop is 2 • 5A • 4mΩ = 40mV. The finished
schematic is shown in Figure 15.
Layout Considerations
There are two considerations for board layout. The first
is that V
IN
and V
DD
bypass capacitors should be as close
to the part as possible. The GND pin should represent the
common tie point. The resistive dividers for UV and OV
should tie here as well.
Take care that current flow to the load (both through V
IN
and GND), does not inadvertently produce errors due to
IR drops in PCB traces.
Keep the traces to the MOSFETs wide and short and close
to the part. The PCB traces associated with the power path
through the MOSFETs should have low resistance.
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