MT89L86 Data Sheet
24
Zarlink Semiconductor Inc.
Interfacing the MT89L86 with 8051
The Intel 8051 is a very cost effective solution for many applications that do not require a large CPU interaction and
processing overhead. However, in applications where 8051 is connected to peripherals operating on a synchronous
8 kHz time-base like the MT89L86, some connectivity issues have to be addressed. The MT89L86 may hold the
CPU read/write cycle due to internal contention between the on-chip microprocessor port and the internal serial-to-
parallel and parallel-to-serial converters. Since the 8051 family of CPUs do not provide Data Ready type of inputs,
some external logic and software intervention have to be provided between the MT89L86 and the 8051
microcontroller to allow read/write operations. The external logic described in Figure 14 is a block diagram of a
logical connection between the MT89L86 and 8051. Its main function is to store the 8051 data during a write and
the MT89L86 data during a read.
For a write, address is latched by the MT89L86’s internal address latch on the falling edge of the ALE input.
Whenever a read or write operation is done to the MT89L86, the address decoded signal (MTA
) is used to latch the
state of RD
, WR, and the ALE signals, until the data acknowledge output signal is provided by the MT89L86,
releasing the latches for a new read/write cycle. Latch U5 is used to hold the 8051 data for a write until the CPU is
ready to accept it (when DTA
goes low). Latch U4 stores the MT89L86 output data during a read cycle whenever
DTA
goes low. When writing to the MT89L86, one write operation is sufficient. However, when reading from the
MT89L86, two read operations with the same address are required, with the second being valid.
