MT89L86AP1 Datasheet MT89L86AP1, MT89L86APR1, MT89L86AN1 | P4-P6

MT89L86 Data Sheet

Zarlink Semiconductor Inc.

22 23 DS/RD Data Strobe/Read (5 V tolerant Input). When the non-multiplexed CPU bus or

Motorola multiplexed bus is selected, this input is DS. This active high input works in

conjunction with CS

to enable read and write operation.

For the Intel/National multiplexed bus interface, this input is RD

. This active low input

configures the data bus lines (AD0-7) as outputs.

23 24 R/W

\WR Read/Write \ Write (5 V tolerant Input). For the non-multiplexed or Motorola

multiplexed bus interface, this input is R/W

. This input controls the direction of the data

bus lines (AD0-AD7) during a microprocessor access.

For the Intel/National multiplexed bus interface, this input is WR

. This active low signal

configures the data bus lines (AD0-7) as inputs.

24 26 CS

Chip Select (5 V tolerant Input). This active low input enables a microprocessor read

or write of the MT89L86’s internal control register or memories.

25-27

29-33

27-29

31-35

AD7-AD0 Data Bus (Bidirectional): These pins provide microprocessor access to the internal

control registers, connection memories high and low and data memories. For the

multiplexed bus interface these pins also provide the input address to the internal

Address Latch circuit.

34 1,

25,37

Ground.

35 38 STo7/A7 ST-BUS Output 7/Address 7 input (Three-state output/input). The function of this pin

is determined by the switching configuration enabled. If non-multiplexed CPU bus is

used along with data rates employing 8.192 Mb/s rates, this pin provides A7 address

input function. For 2.048 Mb/s applications or when the multiplexed CPU bus interface

is selected, this pin assumes STo7 function. See Tables 1, 2, 6 & 7 for more details.

Note that for applications where A7 input and STo7 output are required simultaneously

(e.g., 8.192 to 2.048 Mb/s rate conversion), the A7 input should be connected to pin

STi7/A7.

36 39 STo6/A6 ST-BUS Output 6/Address 6 input (Three-state output/input). The function of this

pin is determined by the switching configuration enabled. If non-multiplexed CPU bus

is used along with a higher data rate employing 8.192 or 4.096 Mb/s, this pin provides

the A6 address input function. For 2.048 Mb/s applications or when the multiplexed

CPU bus interface is selected, this pin assumes STo6 function. See Tables 1, 2, 6 & 7

for more details.

Note that for applications where both A6 input and STo6 output are required

simultaneously (e.g., 4.096 to 2.048 Mb/s or 8.192 to 2.048 Mb/s rate conversion

applications), the A6 input should be connected to pin STi6/A6.

37-39

41-43

40-42

44-46

STo5-0 ST-BUS Outputs 5 to 0 (Three-state Outputs). Serial data output streams. These

serial streams may be composed of 32, 64 and 128 channels at data rates of 2.048,

4.096 or 8.192 Mbit/s, respectively.

44 47 ODE Output Drive Enable (5 V tolerant Input). This is the output enable input for the STo0

to STo9 serial outputs. If this input is low STo0-9 are high impedance. If this input is

high each channel may still be set to high impedance by using per-channel control bits

in Connect Memory High.

Pin Description (continued)

Pin #

Name Description

PLCC

SSOP

MT89L86 Data Sheet

Zarlink Semiconductor Inc.

Device Overview

With the integration of voice, video and data services in the same network, there has been an increasing demand

for systems which ensure that data at N x 64 kb/s rates maintain sequence integrity while being transported through

time-slot interchange circuits. This requirement demands time-slot interchange devices which perform switching

with constant throughput delay for wideband data applications while maintaining minimum delay for voice channels.

The MT89L86 device meets the above requirement and allows existing systems based on the MT8980D to be

easily upgraded to maintain the data integrity when wideband data is transported. The device is designed to switch

32, 64 or N x 64 bit/s data. This MT89L86 can provide frame integrity for data applications and minimum throughput

switching delay for voice applications on a per channel basis.

The serial streams of the MT89L86 can operate at 2.048, 4.096 or 8.192 Mbit/s and are arranged in 125 s wide

frames which contain 32, 64 and 128 channels, respectively. In addition, a built-in rate conversion circuit allows the

user to interconnect various backbone speeds like 2.048 or 4.096 or 8.192 Mb/s while maintaining the control of

throughput delay function on a per-channel basis.

By using Zarlink Message mode capability, the microprocessor can access input and output time-slots on a per

channel basis to control external circuits or other ST-BUS devices. This MT89L86 automatically identifies the

polarity of the frame synchronization input signal and configures its serial port to be compatible to both ST-BUS and

GCI formats.

1 48 CSToControl ST-BUS Output (Output). This is a 2.048 Mb/s output containing 256 bits per

frame. The level of each bit is determined by the CSTo bit in the Connect Memory high

locations.

6 6 AS/ALE Address Strobe or Latch Enable (5 V tolerant Input). This input is only used if

multiplexed bus is selected via the IM input pin.

The falling edge of this signal is used to sample the address into the address latch

circuit. When the non-multiplexed bus interface is selected, this input is not required

and should be connected to ground.

18 19 IM CPU Interface Mode (5 V tolerant Input). If HIGH, this input configures the MT89L86

in the multiplexed microprocessor bus mode. When this input pin is connected to

ground, the MT89L86 assumes non-multiplexed CPU interface.

28 30 STi15/

STo9

ST-BUS Input 15 / ST-BUS Output 9 (Input/three-state output). This pin is only used

if multiplexed CPU bus is selected. If 16-input x 8-output switching configuration is

enabled in the SCB bits (IMS register), this pin is an input receiving serial ST-BUS

stream 15 at a data rate of 2.048 Mbit/s.

If Stream Pair Selection capability is enabled (see switching configuration section), this

pin is the ST-BUS stream 9 output.

When non-multiplexed bus structure is used, this pin should be connected to ground.

40 43 STi14/

STo8

ST-BUS Input 14 / ST-BUS Output 8 (Input/three-state output). This pin is only used

if multiplexed CPU bus is selected. If 16-input x 8-output switching configuration is

enabled in the SCB bits (IMS register), this pin is an input that receives serial ST-BUS

stream 14 at a data rate of 2.048 Mbit/s.

If Stream Pair Selection capability is enabled (see switching configuration section), this

pin is the ST-BUS stream 8 output.

When non-multiplexed bus structure is used, this pin should be connected to ground.

Pin Description (continued)

Pin #

Name Description

PLCC

SSOP

MT89L86 Data Sheet

Zarlink Semiconductor Inc.

Two different microprocessor bus interfaces can be selected through an input mode pin (IM): Non-Multiplexed or

Multiplexed. These interfaces provide compatibility with Intel/National multiplexed and Motorola Multiplexed/Non-

Multiplexed buses. The MT89L86 provides a 16 x 8 switching configuration to form a 512 x 256 channel blocking

matrix. Also, a flexible Stream Pair Selection operation allows the software selection of which pair of input and

output streams can be connected to an internal 128 x 128 matrix. See Switching Configurations section for details.

Functional Description

A functional Block Diagram of the 3.3 V MT89L86 is shown in Figure 1. Depending on the application, TDM serial

data can be received at different rates and from different number of serial streams.

Data and Connect Memories

For all data rates, the received serial data is converted to parallel format by the serial to parallel converters and

stored sequentially in a Data Memory. Depending on the selected operation programmed in the IMS (Interface

Mode Select) register, the Data Memory may have up to 512 bytes in use. The sequential addressing of the Data

Memory is performed by an internal counter which is reset by the input 8 kHz frame pulse (FR) marking the frame

boundaries of the incoming serial data streams.

Data to be output on the serial streams may come from two sources: Data Memory or Connect Memory. Locations

in the Connect Memory, which is split into HIGH and LOW parts, are associated with particular ST-BUS output

streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either be

switched from an ST-BUS input as in connection mode or it can be from the Connect Memory Low as in message

mode. Data destined for a particular channel on the serial output stream is read from the Data Memory or Connect

Memory Low during the previous channel time-slot. This allows enough time for memory access and parallel to

serial conversion.

Connection and Message Modes

In the connection mode, the addresses of the input source data for all output channels are stored in the Connect

memories High (CMH) and Low (CML). The CML and CMH are mapped so that each location corresponds to an

output channel on the output streams. The number of source address bits in CMH and CML to be utilized varies

according to the switching configuration selected in the IMS register. For details on the use of the source address

data (CAB and SAB bits), see CMH and CML bit describe-thin (Figures 5 & 6). Once the source address bits are

programmed by the CPU, the contents of the Data Memory at the selected address are transferred to the parallel-

to-serial converters. By having the output channel specify the source channel through the connect memory, the

user can route the same input channel to several output channels, allowing broadcast facility within the switch.

In the message mode the CPU writes data to the Connect Memory Low locations corresponding to the output link

and channel number. The contents of the Connect Memory Low are transferred directly to the parallel-to-serial

converter one channel before it is to be output. The Connect Memory Low data is transmitted on to the output every

frame until it is changed by the CPU with a new data.

The features of each output channel in the 3.3 V MT89L86 are controlled by the Connect Memory High bits. These

bits determine individual output channels to be in message or connection mode, select throughput delay types and

enable/disable output drivers. The Connect Memory High also provides additional stream and channel address bits

for some configurations. In addition, the Connect Memory High provides one bit to allow the user to control the CST

output in 2.048 Mb/s applications.

If an output channel is set to high-impedance, the TDM serial stream output will be placed in high impedance during

that channel time. In addition to the per-channel control, all channels on the TDM outputs can be placed in high

impedance by pulling the ODE input pin LOW. This overrides the individual per-channel programming by the

Connect Memory High bits.

The Connect Memory data is received via the Microprocessor Interface through the data I/O lines. The addressing

of the MT89L86 internal registers, Data and Connect memories is performed through address input pins and some

bits of the device's Control register. The higher order address bits come from the Control register, which may be

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MT89L86AP1

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MT89L86AP1

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