Data Sheet ADP195
Rev. C | Page 9 of 12
THEORY OF OPERATION
GND
EN
VIN
VOUT
ADP195
LEVEL SHIFT
AND SLEW
RATE CONTROL
08679-025
REVERSE
POLARITY
PROTECTION
Figure 21. Functional Block Diagram
The ADP195 is a high-side PMOS load switch. It is designed for
supply operation between 1.1 V to 3.6 V. The PMOS load switch
is designed for low on resistance, 65 mΩ at V
IN
= 1.8 V and
supports greater than 1 A of continuous current. It is a low
quiescent current device with a nominal 4 MΩ pull-down
resistor on its enable pin (EN).
The reverse current protection circuitry prevents current flow
backward through the ADP195 when the output voltage is greater
than the input voltage. A comparator senses the difference
between the input and output voltages. When the difference
between the input voltage and output voltage exceeds 75 mV,
the body of the pFET is switched to V
OUT
and is turned off or
opened; that is, the gate is connected to V
OUT
.
The packaging is a space-saving 1.0 mm × 1.0 mm, 4-ball WLCSP.
The ADP195 is also available in a 2 mm × 2 mm × 0.55 mm,
0.65 mm pitch LFCSP.
ADP195 Data Sheet
Rev. C | Page 10 of 12
APPLICATIONS INFORMATION
GROUND CURRENT
The major source for ground current in the ADP195 is an internal
4 MΩ pull-down on the enable pin. Figure 22 shows the typical
ground current when V
EN
= V
IN
and varies from 1.2 V to 3.6 V.
0
2
4
6
8
10
0 50 100 150 200 250 300 350 400 450 500
LOAD (mA)
GROUND CURRENT (µA)
08679-017
V
IN
= 1.2V
V
IN
= 1.6V
V
IN
= 2.0V
V
IN
= 2.4V
V
IN
= 2.8V
V
IN
= 3.2V
V
IN
= 3.4V
V
IN
= 3.6V
Figure 22. Ground Current vs. Load Current
As shown in Figure 23, an increase in quiescent current can occur
when V
EN
≠ V
IN
. This is caused by the CMOS logic nature of the
level shift circuitry as it translates an V
EN
signal ≥ 1.2 V to a
logic high. This increase is a function of the V
IN
− V
EN
delta.
0
2
4
6
8
10
12
14
16
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6
V
EN
(V)
I
GND
(
µA)
V
IN
= 1.2V
V
IN
= 1.5V
V
IN
= 1.8V
V
IN
= 2.5V
V
IN
= 3.6V
08679-018
Figure 23. Typical Ground Current when V
EN
≠ V
IN
ENABLE FEATURE
The ADP195 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. As shown in Figure 24,
when a rising voltage on V
EN
crosses the active threshold, V
OUT
turns on. When a falling voltage on V
EN
crosses the inactive
threshold, V
OUT
turns off.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.20 0.4 0.5 0.6 0.70.1 0.2 0.3 0.8 0.9 1.0 1.1
V
EN
(V)
V
OUT
(V)
08679-019
Figure 24. Typical EN Operation
As shown in Figure 24, the EN pin has hysteresis built in. This
prevents on/off oscillations that can occur due to noise on the
EN pin as it passes through the threshold points.
The EN pin active/inactive thresholds derive from the V
IN
voltage;
therefore, these thresholds vary with the changing input voltage.
Figure 25 shows the typical EN active/inactive thresholds when
the input voltage varies from 1.2 V to 3.6 V.
1.15
1.05
0.95
0.85
0.75
0.65
0.55
0.45
0.35
3.60
1.20
1.35
1.50
1.65
1.80
1.95
2.10
2.25
2.40
2.55
2.70
2.85
3.00
3.15
3.30
3.45
V
IN
(V)
TYPICAL EN THRESHOLDS (V)
EN ACTIVE
EN INACTIVE
08679-020
Figure 25. Typical EN Thresholds vs. Input Voltage (V
IN
)
Data Sheet ADP195
Rev. C | Page 11 of 12
TIMING
Turn-on delay is defined as the delta between the time that V
EN
reaches >1.2 V until V
OUT
rises to ~10% of its final value. The
ADP195 includes circuitry to have typical 5 μs turn-on delay at
3.6 V V
IN
to limit the V
IN
inrush current. As shown in Figure 26,
the turn-on delay is dependent on the input voltage.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 5 10 15 20 25 30 35 40
TIME (µs)
VOL
T
AGE (V)
V
EN
V
IN
= 1.2V
V
IN
= 1.8V
V
IN
= 2.5V
V
IN
= 3.6V
08679-021
Figure 26. Typical Turn-On Delay Time with Varying Input Voltage
The rise time is defined as the delta between the time from
10% to 90% of V
OUT
reaching its final value. It is dependent on
the RC time constant where C = load capacitance (C
LOAD
) and
R = RDS
ON
||R
LOAD
. Because RDS
ON
is usually smaller than R
LOAD
,
an adequate approximation for RC is RDS
ON
× C
LOAD
. An input
or load capacitor is not needed for the ADP195; however, capacitors
can be used to suppress noise on the board. If significant load
capacitance is connected, inrush current is a concern.
CH1 2V CH2 1V M4µs A CH1 2.32V
2
3
1
T 10%
V
EN
B
W
CH3 200mA B
W
V
OUT
LOAD CURRENT
08679-022
B
W
Figure 27. Typical Rise Time and Inrush Current,
C
LOAD
= 1 μF, V
IN
= 1.8 V, No Load
CH1 2V CH2 1V M4µs A CH1 2.32V
2
3
1
T 10%
V
EN
B
W
CH3 200mA B
W
V
OUT
LOAD CURRENT
08679-023
Figure 28. Typical Rise Time and Inrush Current,
C
LOAD
= 1 μF, V
IN
= 1.8 V, Load = 200 mA
The turn-off time is defined as the delta between the time from
90% to 10% of V
OUT
reaching its final value. It is also dependent on
the RC time constant.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 20406080100
TIMEs)
VOLTAGE (V)
V
EN
V
OUT
AT 200mA
V
OUT
AT 100mA
08679-024
Figure 29. Typical Turn-Off Time

ADP195ACPZ-R7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - Power Distribution Logic Cntrld Hi Side Pwr Switch
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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