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MTP12P10G

P1-P3P4-P6
MTP12P10
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4
SAFE OPERATING AREA INFORMATION
I
D
, DRAIN CURRENT (AMPS)
I
D
, DRAIN CURRENT (AMPS)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Maximum Rated Forward Biased
Safe Operating Area
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 8. Maximum Rated Switching
Safe Operating Area
02040 6080
0
40
50
100
R
DS(on)
LIMIT
PACKAGE LIMIT
THERMAL LIMIT
10
V
GS
= 20 V
SINGLE PULSE
T
C
= 25°C
1
1
10
10 ms
1 ms
10 ms
30
10
100
0.1 ms
MTM/MTP12P06
MTM/MTP12P10
20
10 30 50 70 90
MTM/MTP12P06
MTM/MTP12P10
dc
FORWARD BIASED SAFE OPERATING AREA
The FBSOA curves define the maximum drain−to−source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned
on. Because these curves include the limitations of
simultaneous high voltage and high current, up to the rating
of the device, they are especially useful to designers of linear
systems. The curves are based on a case temperature of 25°C
and a maximum junction temperature of 150°C. Limitations
for repetitive pulses at various case temperatures can be
determined by using the thermal response curves. ON
Semiconductor Application Note, AN569, “Transient
Thermal Resistance−General Data and Its Use” provides
detailed instructions.
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 8 is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the
peak current, I
DM
and the breakdown voltage, V
(BR)DSS
.
The switching SOA shown in Figure 8 is applicable for both
turn−on and turn−off of the devices for switching times less
than one microsecond.
The power averaged over a complete switching cycle
must be less than:
T
J(max)
− T
C
R
q
JC
Figure 9. Thermal Response
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
R
q
JC
(t) = r(t) R
q
JC
R
q
JC
= 1.67°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
− T
C
= P
(pk)
R
q
JC
(t)
P
(pk)
t
1
t
2
DUTY CYCLE, D = t
1
/t
2
t, TIME (ms)
1
0.01
D = 0.5
0.05
0.01
SINGLE PULSE
0.01
0.02
0.03
0.02
0.05
0.1
0.2
0.3
0.5
0.02 0.05 0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 1000
0.1
0.2
MTP12P10
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5
V
DS
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
Figure 10. Capacitance Variation
1600
4030
1200
800
400
0
20
100
T
C
= 25°C
V
GS
= 0
f = 1 MHz
C
oss
C
iss
C
rss
0 5 10 15 20 25 30 35 40 45 50
Q
g
, TOTAL GATE CHARGE (nC)
Figure 11. Gate Charge versus
Gate−To−Source Voltage
T
J
= 25°C
I
D
= 12 A
V
DS
= 30 V
80 V
50 V
V
GS
, GATE SOURCE VOLTAGE (VOLTS)
0
−2
−4
−6
−8
−10
−12
−14
−16
RESISTIVE SWITCHING
PULSE GENERATOR
V
DD
V
out
V
in
R
gen
50 W
z = 50 W
50 W
DUT
R
L
Figure 12. Switching Test Circuit
t
off
OUTPUT, V
out
t
on
t
r
t
d(off)
t
f
t
d(on)
90%90%
10%
INPUT, V
in
10%
50%
90%
50%
PULSE WIDTH
Figure 13. Switching Waveforms
INVERTED
MTP12P10
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6
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AB
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.570 0.620 14.48 15.75
B 0.380 0.405 9.66 10.28
C 0.160 0.190 4.07 4.82
D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73
G 0.095 0.105 2.42 2.66
H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33
Q 0.100 0.120 2.54 3.04
R 0.080 0.110 2.04 2.79
S 0.020 0.055 0.508 1.39
T 0.235 0.255 5.97 6.47
U 0.000 0.050 0.00 1.27
V 0.045 −−− 1.15 −−−
Z −−− 0.080 −−− 2.04
B
Q
H
Z
L
V
G
N
A
K
F
123
4
D
SEATING
PLANE
−T−
C
S
T
U
R
J
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MTP12P10/D
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P1-P3P4-P6

MTP12P10G

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MOSFET P-CH 100V 12A TO220AB
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