7
LTC1553L
PIN FUNCTIONS
UUU
VID0, VID1, VID2, VID3, VID4 (Pins 18, 17, 16, 15, 14):
Digital Voltage Select. TTL inputs used to set the regulated
output voltage required by the processor (Table 3). There
is an internal 20k pull-up at each pin. When all five VID
n
pins are high or floating, the chip will shut down.
OUTEN (Pin 19): Output Enable. TTL input which enables
the output voltage. The external MOSFET temperature can
be monitored with an external thermistor as shown in
Figure 11. When the OUTEN input voltage drops below 2V,
OT trips. As OUTEN drops below 1.7V, the drivers are
internally disabled to prevent the MOSFETs from heating
further. If OUTEN is less than 1.2V for longer than 30µs,
the LTC1553L will enter shutdown mode. The internal
oscillator can be synchronized to a faster external clock by
applying the external clocking signal to the OUTEN pin.
G1 (Pin 20): Gate Drive for the Upper N-Channel MOSFET,
Q1. This output will swing from PV
CC
to GND. It will always
be low when G2 is high or the output is disabled.
BLOCK DIAGRAM
W
VID0
VID1
VID2
VID3
VID4
18
17
16
15
14
OUTEN
19
COMP
SS
PV
CC
G1
G2
1553 BD
SENSE
+
FC
+
+
PWM
SYSTEM
POWER
DOWN
R
S
DISDR
V
REF
I
SS
Q
SS
115% V
REF
V
REF
0.5V
REF
/
0.7V
REF
HCL MONOMHCL
V
REF
– 5% V
REF
+ 5%
DELAY
DAC
FB
LOGIC
MAX
+
MIN
+
ERR
+
I
MAX
I
MAX
I
FB
PWRGD
CC
+
LVC
FAULT
OT
BG
10
9
12
11
13
2
20
1
6
8
7
8
LTC1553L
TEST CIRCUITS
Figure 4
Figure 3
Figure 2
OUTEN
PWRGD
FAULT
OT
VID0 TO VID4
COMP
SS SGND GND SENSE
Q1*
NC
Q2*
V
CC
I
FB
PV
CC
12V
V
CC
5V
PV
CC
V
IN
5V
L
O
2µH
15A
LTC1553L
G1
I
MAX
G2
0.1µF
1553L F02
C
C
0.01µF
R
C
8.2k
3k
100pF
0.1µF
0.1µF
0.1µF
10µF
10µF
V
OUT
+
C1
150pF
10k
3k3k
++
VID0 TO VID4
100pF
100pF
+
C
IN
**
1200µF
× 4
*SILICONIX SUD50N03-10
**SANYO 10MV1200GX
COILTRONICS CTX02-13198 OR
 PANASONIC 12TS-2R5SP
††
AVX TPSE337M006R0100
C
OUT
††
330µF
× 7
OUTEN
PWRGD
FAULT
OT
COMP
SS SGND GND SENSE
10µF
NC
NC
NC
NC
NC
NC
NC
NC
0.1µF
V
CC
V
CC
V
CC
VID0 VID1 VID2 VID3 VID4
VID0 VID1 VID2 VID3 VID4
I
FB
PV
CC
LTC1553L
PV
CC
G1
I
MAX
G2
1553L F03
0.1µF
10µF
+
+
10k
V
CC
5V
PV
CC
12V
0.1µF
10µF
G2 RISE/FALL
G1 RISE/FALL
5000pF
5000pF
SGND GND
SENSE
10µF
G2
G1
0.1µF
V
CC
I
FB
LTC1553L
PV
CC
1553L F04
90%
t
r
t
f
t
NOL
t
NOL
50%
10%
50% 50%
90%
50%
10%
+
+
10k
9
LTC1553L
FU CTIO TABLES
U U
Table 1. OT Logic
OUTEN (V) OT*
< 2 0
> 2 1
Table 2. PWRGD and FAULT Logic
INPUT OUTPUT*
OUTEN V
SENSE
** OT FAULT PWRGD
0 X 010
1 < 95% 1 1 0
1 > 95% 1 1 1
< 105%
1 >105% 1 1 0
1 > 115% 1 0 0
Table 3. Rated Output Voltage
INPUT PIN
RATED OUTPUT
V
ID4
V
ID3
V
ID2
V
ID1
V
ID0
VOLTAGE (V)
01111Disabled
(1.30)
01110Disabled
(1.35)
01101Disabled
(1.40)
01100Disabled
(1.45)
01011Disabled
(1.50)
01010Disabled
(1.55)
01001Disabled
(1.60)
01000Disabled
(1.65)
00111Disabled
(1.70)
00110Disabled
(1.75)
00101 1.80
00100 1.85
00011 1.90
00010 1.95
00001 2.00
00000 2.05
11111 SHDN
11110 2.1
11101 2.2
11100 2.3
11011 2.4
11010 2.5
11001 2.6
11000 2.7
10111 2.8
10110 2.9
10101 3.0
10100 3.1
10011 3.2
10010 3.3
10001 3.4
10000 3.5
* With external pull-up resistor
** With respect to the output voltage selected in Table 3 as required by
Intel Specification VRM 8.2
These code selections are disabled in LTC1553L
X Don’t care
Table 3. Rated Output Voltage (cont)
INPUT PIN
RATED OUTPUT
V
ID4
V
ID3
V
ID2
V
ID1
V
ID0
VOLTAGE (V)

LTC1553LCSW#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 5-B Progmable Sync Sw Reg Cntr for Penti
Lifecycle:
New from this manufacturer.
Delivery:
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