TB62747AFG/AFNG/AFNAG/BFNAG
2009-01-21
4
Truth Table
SCK
SLAT
OE
SIN
OUT0
OUT7
OUT15
*1 SOUT
H L Dn Dn … Dn 7 … Dn 15 Dn 15
L L Dn + 1 No Change Dn 14
H L Dn + 2 Dn + 2 … Dn 5 … Dn 13 Dn 13
*2 L Dn + 3 Dn + 2 … Dn 5 … Dn 13 Dn 13
*2 H Dn + 3 OFF Dn 13
Note1: When
OUT0
to
OUT15
output pins are set to "H" the respective output will be ON and when set to
"L" the respective output will be OFF.
Note2: “-“ is irrelevant to the truth table.
Timing Diagram
Note 1: The latch circuit is a leveled-latch circuit. Please exercise precaution as it is not triggered-latch circuit.
Note 2: Keep the
SLAT
pin is set to “L” to enable the latch circuit to hold data. In addition, when the
SLAT
pin
is set to “H” the latch circuit does not hold data. The data will instead pass onto output.
When the
OE
pin is set to “L” the
OUT0
to
OUT15
output pins will go ON and OFF in response to
the data. In addition, when the
OE
pin is set to “H” all the output pins will be forced OFF regardless of
the data.
SIN
SLAT
SCK
OUT0
OUT1
SOUT
OE
OUT15
H
L
n
=
0
1
2
3
4
5
6
8
H
L
H
L
H
L
ON
OFF
ON
OFF
ON
OFF
ON
OFF
H
L
7
9
11
10
12
13
15
14
2OUT
TB62747AFG/AFNG/AFNAG/BFNAG
2009-01-21
5
Pin Functions
Pin No
Pin Name I/O Function
AFG
AFNG
AFNAG
BFNAG
1 7 GND The ground pin.
2 8 SIN I The serial data input pin.
3 9 SCK I The serial data transfer clock input pin.
4 10
SLAT
I
The latch signal input pin.
Data is saved at L level.
5 11
OUT0
O A sink type constant current output pin.
6 12
OUT1
O A sink type constant current output pin.
7 13
OUT2
O A sink type constant current output pin.
8 14
OUT3
O A sink type constant current output pin.
9 15
OUT4
O A sink type constant current output pin.
10 16
OUT5
O A sink type constant current output pin.
11 17
OUT6
O A sink type constant current output pin.
12 18
OUT7
O A sink type constant current output pin.
13 19
OUT8
O A sink type constant current output pin.
14 20
OUT9
O A sink type constant current output pin.
15 21
OUT10
O A sink type constant current output pin.
16 22
OUT11
O A sink type constant current output pin.
17 23
OUT12
O A sink type constant current output pin.
18 24
OUT13
O A sink type constant current output pin.
19 1
OUT14
O A sink type constant current output pin.
20 2
OUT15
O A sink type constant current output pin.
21 3
OE
I
The constant current output enable signal input pin.
During the “H” level, the output will be forced off.
22 4 SOUT O The serial data output pin.
23 5 R
EXT
The constant current value setting resistor connection pin.
24 6 V
DD
The power supply input pin.
TB62747AFG/AFNG/AFNAG/BFNAG
2009-01-21
6
Absolute Maximum Ratings (T
a
=
25°C)
Characteristics Symbol Rating *1 Unit
Power supply voltage V
DD
0.4 to 6.0 V
Output current I
O
55 mA
Logic input voltage V
IN
0.3 to V
DD
+ 0.3 *2 V
Output voltage V
O
0.3 to 26 V
Operating temperature T
opr
40 to 85 °C
Storage temperature T
stg
55 to 150 °C
Thermal resistance
Rth(j-a)
94 (AFG) *3, 120 (AFNG) *3, 80.07(AFNAG/BFNAG)
When mounted PCB
°C/W
Power dissipation P
D
*4
1.32 (AFG) *3, 1.04 (AFNG) *3, 1.56(AFNAG/BFNAG)
When mounted PCB
W
Note1: Voltage is ground referenced.
Note2: However, do not exceed 6V.
Note3: PCB condition 76.2 x 114.3 x 1.6 mm, Cu 30% (SEMI conforming)
Note4: The power dissipation decreases the reciprocal of the saturated thermal resistance (1/ Rth(j-a)) for each
degree (1°C) that the ambient temperature is exceeded (Ta = 25°C).
Operating Conditions
DC Items (Unless otherwise specified, V
DD
= 3.0 to 5.5 V, T
a
=
40°C to 85°C)
Characteristics Symbol Test Conditions Min Typ. Max Unit
Power supply voltage V
DD
3.0 5.5 V
Output voltage when OFF V
O (ON)
OUTn
0.4 4.0 V
High level logic input voltage V
IH
SIN,SCK,
SLAT
,
OE
0.7 ×
V
DD
V
DD
V
Low level logic input voltage V
IL
SIN,SCK,
SLAT
,
OE
GND
0.3 ×
V
DD
V
High level SOUT output current I
OH
1 mA
Low level SOUT output current I
OL
1 mA
Constant current output
I
O1
OUTn
, V
DD
= 3.3 V, V
O
= 0.4 to 1.0 V 1.5 35
mA
I
O2
OUTn
, V
DD
= 5.0 V, V
O
= 0.4 to 1.2 V 1.5 45
AC Items (Unless otherwise specified, V
DD
= 3.0 to 5.5 V, T
a
=
40°C to 85°C)
Characteristics Symbol
Test
Circuits
Test Conditions Min Typ. Max Unit
Serial data transfer frequency f
SCK
6 25 MHz
Hold time
t
HOLD1
6 5 ns
t
HOLD2
6 5 ns
Setup time
t
SETUP1
6 5 ns
t
SETUP2
6 5 ns
Maximum clock rise time t
r
6 *1 500 ns
Maximum clock fall time t
f
6 *1 500 ns
Note1: If the device is connected in a cascade and the tr/tf of the clock waveform increases due to deceleration of the clock
waveform,it may not be possible to achieve the timing required for data transfer. Please keep these timing conditions in mind
when designing your application.

TB62747AFNAG,EL

Mfr. #:
Manufacturer:
Description:
IC LED DVR 16CH CC 24SSOP
Lifecycle:
New from this manufacturer.
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