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TB62747AFNAG,EL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
TB62747AFG/AFNG/AFNAG/BFNAG
2009-01-21
7
Electrical Characteristics (Unless otherwise specified, V
DD
= 3.3V, T
a
= 25°C)
Characteristics Symbol
Test
Circuits
Test Conditions Min Typ. Max Unit
High level logic output voltage V
OH
1 I
OH
= −1 mA
V
DD
−
0.4
V
Low level logic output voltage V
OL
1 I
OL
= +1 mA 0.4 V
High level logic input current I
IH
2 V
IN
= V
DD
,
OE
, SIN, SCK 1 µA
Low level logic input current I
IL
3 V
IN
= GND,
SLAT
, SIN, SCK −1 µA
Power supply current
I
DD1
4
V
O
= 25 V, R
EXT
= OPEN,
SCK
= “L”,
OE
= “H”
1.0 mA
I
DD2
4 R
EXT
= 1.2 kΩ, All output off 4.0 mA
I
DD3
4 R
EXT
= 1.2 kΩ, All output on 8.0 mA
Output current I
O
5
V
DD
= 3.3 V, V
O
= 0.4 V,
R
EXT
= 1.2 kΩ,
OUT0
to
OUT15
14 mA
Constant current error(Ch to Ch) ∆I
O
5
V
DD
= 3.3 V, V
O
= 0.4 V,
R
EXT
= 1.2 kΩ,
OUT0
to
OUT15
±1 ±1.5 %
Constant current error(IC to IC) ∆I
O(IC)
5
V
DD
= 3.3 V, V
O
= 0.4 V,
R
EXT
= 1.2 kΩ,
OUT0
to
OUT15
±1 ±1.5 %
Output OFF leak current I
OK
5
V
DD
= 3.3 V, V
O
= 25 V,
R
EXT
= 1.2 k
Ω
,
OUT0
to
OUT15
0.5 µA
Constant current power supply voltage
regulation
%V
DD
5
V
DD
= 3.0 to 3.6 V, V
O
= 0.4 V,
R
EXT
= 1.2 k
Ω
,
OUT0
to
OUT15
±1 ±2 %
Constant current output voltage
regulation
%V
O
5
V
DD
= 3.3 V, V
O
= 0.4 to 3.0 V,
R
EXT
= 1.2 kΩ,
OUT0
to
OUT15
±1 %/V
Pull-up resistor R
UP
3
OE
250 500 800 kΩ
Pull-down resistor R
DOWN
2
SLAT
250 500 800 kΩ
Electrical Characteristics (Unless otherwise specified, V
DD
= 5.0V, T
a
= 25°C)
Characteristics Symbol
Test
Circuits
Test Conditions Min Typ. Max Unit
High level logic output voltage V
OH
1 I
OH
= −1 mA
V
DD
−
0.4
V
Low level logic output voltage V
OL
1 I
OL
= +1 mA 0.4 V
High level logic input current I
IH
2 V
IN
= V
DD
,
OE
, SIN, SCK 1 µA
Low level logic input current I
IL
3 V
IN
= GND,
SLAT
, SIN, SCK −1 µA
Power supply current
I
DD1
4
V
O
= 25 V, R
EXT
= OPEN,
SCK
= “L”,
OE
= “H”
1.0 mA
I
DD2
4 R
EXT
= 1.2 kΩ, All output off 4.5 mA
I
DD3
4 R
EXT
= 1.2 kΩ, All output on 8.0 mA
Output current I
O
5
V
DD
= 5.0 V, V
O
= 0.4 V,
R
EXT
= 1.2 kΩ,
OUT0
to
OUT15
14 mA
Constant current error(Ch to Ch) ∆I
O
5
V
DD
= 5.0 V, V
O
= 0.4 V,
R
EXT
= 1.2 k
Ω
,
OUT0
to
OUT15
±1 ±1.5 %
Constant current error(IC to IC) ∆I
O(IC)
5
V
DD
= 5.0 V, V
O
= 0.4 V,
R
EXT
= 1.2 k
Ω
,
OUT0
to
OUT15
±1 ±1.5 %
Output OFF leak current I
OK
5
V
DD
= 5.0 V, V
O
= 25 V,
R
EXT
= 1.2 kΩ,
OUT0
to
OUT15
0.5 µA
Constant current power supply voltage
regulation
%V
DD
5
V
DD
= 4.5 to 5.5 V, V
O
= 0.4 V,
R
EXT
= 1.2 k
Ω
,
OUT0
to
OUT15
±1 ±2 %
Constant current output voltage
regulation
%V
O
5
V
DD
= 5.0 V, V
O
= 0.4 to 3.0 V,
R
EXT
= 1.2 kΩ,
OUT0
to
OUT15
±1 %/V
Pull-up resistor R
UP
3
OE
250 500 800 kΩ
Pull-down resistor R
DOWN
2
SLAT
250 500 800 kΩ
TB62747AFG/AFNG/AFNAG/BFNAG
2009-01-21
8
Switching Characteristics (Unless otherwise specified, V
DD
= 3.3V, T
a
= 25°C)
Characteristics Symbol
Test
Circuits
Test Conditions Min Typ. Max Unit
Propagation delay
time
SCK-
OUT0
t
pLH1
6
SLAT
= “H”,
OE
= “L” 20 300 ns
SLAT
-
OUT0
t
pLH2
6
OE
= “L” 20 300 ns
OE
-
OUT0
t
pLH3
6
SLAT
= “H” 20 300 ns
SCK-SOUT t
pLH
6 CL=10.5 pF 10 20 35 ns
SCK-
OUT0
t
pHL1
6
SLAT
= “H”,
OE
= “L” 30 340 ns
SLAT
-
OUT0
t
pHL2
6
OE
= “L” 70 340 ns
OE
-
OUT0
t
pHL3
6
SLAT
= “H” 70 340 ns
SCK-SOUT t
pHL
6 CL=10.5 pF 10 20 35 ns
Output rise time t
or
6 10 to 90% of voltage waveform 20 90 ns
Output fall time t
of
6 90 to 10% of voltage waveform 25 180 ns
Enable pulse width t
wOE(L)
6
OE
= “L” *1
100 ns
Clock pulse width t
wSCK
6 SCK
= “H” or “L” 20 ns
Latch pulse width t
wSLAT
6
SLAT
= “H” 20 ns
Note1: At the condition of t
wOE(H)
= 250ns or more
Switching Characteristics (Unless otherwise specified, V
DD
= 5.0V, T
a
= 25°C)
Characteristics Symbol
Test
Circuits
Test Conditions Min Typ. Max Unit
Propagation delay
time
SCK-
OUT0
t
pLH1
6
SLAT
= “H”,
OE
= “L” 20 300 ns
SLAT
-
OUT0
t
pLH2
6
OE
= “L” 20 300 ns
OE
-
OUT0
t
pLH3
6
SLAT
= “H” 20 30 ns
SCK-SOUT t
pLH
6 CL=10.5 pF 10 20 35 ns
SCK-
OUT0
t
pHL1
6
SLAT
= “H”,
OE
= “L” 30 340 ns
SLAT
-
OUT0
t
pHL2
6
OE
= “L” 70 340 ns
OE
-
OUT0
t
pHL3
6
SLAT
= “H” 70 340 ns
SCK-SOUT t
pHL
6 CL=10.5 pF 10 20 35 ns
Output rise time t
or
6 10 to 90% of voltage waveform 20 90 ns
Output fall time t
of
6 90 to 10% of voltage waveform 25 180 ns
Enable pulse width t
wOE(L)
6
OE
= “L” *1
100 ns
Clock pulse width t
wSCK
6 SCK
= “H” or “L” 20 ns
Latch pulse width t
wSLAT
6
SLAT
= “H” 20 ns
Note1: At the condition of t
wOE(H)
= 250ns or more
TB62747AFG/AFNG/AFNAG/BFNAG
2009-01-21
9
I/O Equivalent Circuits
1. SCK, SIN 2.
OE
3.
SLAT
4. SOUT
5.
OUT0
to
OUT15
V
DD
SOUT
GND
V
DD
(SCK)
(SIN)
V
DD
OE
V
DD
SLAT
GND
GND
OUT0
to
15OUT
GND
GND
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

TB62747AFNAG,EL

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IC LED DVR 16CH CC 24SSOP
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