NTHD4401PT3G

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TYPICAL PERFORMANCE CURVES (T
J
= 25°C unless otherwise noted)
V
DS
= 0 V V
GS
= 0 V
−V
GS
510 10
600
300
200
100
0
20
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLT
S)
C, CAPACITANCE (pF)
02
6
1
4
1
0
Q
g
, TOTAL GATE CHARGE (nC)
−V
GS,
GATE−TO−SOURCE VOLTAGE (VOLTS)
T
J
= 25°C
C
oss
C
iss
C
rss
I
D
= −2.1 A
T
J
= 25°C
QT
500
32.5
2
3
−V
DS,
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
12
10
8
2
0
Q2Q1
101
10
1
10
0
R
G
, GATE RESISTANCE (OHMS)
t, TIME (ns)
V
DD
= −16 V
I
D
= −2.1 A
V
GS
= −4.5 V
100
50
400
5
4
6
t
d(off)
t
d(on)
t
f
t
r
−V
GS
−V
DS
−V
DS
15
1.50.5 3.5
0.9
0.5
0
−V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
−I
S
, SOURCE CURRENT (AMPS)
V
GS
= 0 V
T
J
= 25°C
2.5
0.70.50.3
1
1.5
2
24 8
10
2016
Figure 7. Drain−to−Source Leakage Current
vs. Voltage
−V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
12
V
GS
= 0 V
−I
DSS
, LEAKAGE (A)
T
J
= 150°C
T
J
= 100°C
100
1000
10000
610 1814
Figure 8. Capacitance Variation
Figure 9. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Figure 10. Resistive Switching Time Variation
vs. Gate Resistance
Figure 11. Diode Forward Voltage vs. Current
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5
t, TIME (s)
Figure 12. Thermal Response
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1.0
0.1
0.01
0.2
D = 0.5
0.05
0.01
SINGLE PULSE
0.1
1.0E−03 1.0E−02 1.0E−01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
0.02
0.0175 Ω 0.0710 Ω 0.2706 Ω 0.5776 Ω 0.7086 Ω
107.55 F1.7891 F0.3074 F0.0854 F0.0154 F
Chip
Ambient
Normalized to θJA at 10s.
0.457
0.018
2.032
0.08
0.635
0.025
0.66
0.026
0.711
0.028
ǒ
mm
inches
Ǔ
SCALE 20:1
0.457
0.018
2.032
0.08
0.635
0.025
0.66
0.026
0.254
0.010
ǒ
mm
inches
Ǔ
SCALE 20:1
1.092
0.043
0.178
0.007
Figure 13. Basic Figure 14. Style 2
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in
Figure 13. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area, particularly
for the drain leads.
The minimum recommended pad pattern shown in
Figure 14 improves the thermal area of the drain
connections (pins 5, 6, 7, 8) while remaining within the
confines of the basic footprint. The drain copper area is
0.0019 sq. in. (or 1.22 sq. mm). This will assist the power
dissipation path away from the device (through the copper
leadframe) and into the board and exterior chassis (if
applicable) for the single device. The addition of a further
copper area and/or the addition of vias to other board layers
will enhance the performance still further.
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PACKAGE DIMENSIONS
ChipFET]
CASE 1206A−03
ISSUE G
STYLE 2:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
E
A
b
e
e1
D
1234
8765
c
L
1234
8765
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.
0.05 (0.002)
DIM
A
MIN NOM MAX MIN
MILLIMETERS
1.00 1.05 1.10 0.039
INCHES
b 0.25 0.30 0.35 0.010
c 0.10 0.15 0.20 0.004
D 2.95 3.05 3.10 0.116
E 1.55 1.65 1.70 0.061
e 0.65 BSC
e1 0.55 BSC
L 0.28 0.35 0.42 0.011
0.041 0.043
0.012 0.014
0.006 0.008
0.120 0.122
0.065 0.067
0.025 BSC
0.022 BSC
0.014 0.017
NOM MAX
1.80 1.90 2.00 0.071 0.075 0.079
H
E
5° NOM
q
5° NOM
H
E
q
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ChipFET is a trademark of Vishay Siliconix.
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NTHD4401PT3G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
MOSFET -20V -3A Dual P-Channel
Lifecycle:
New from this manufacturer.
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