IRFH8318TRPBF

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IRFH8318PbF
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case (Bottom)
Fig 8. Maximum Safe Operating Area
Fig 9. Maximum Drain Current vs.
Case (Bottom) Temperature
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 10. Threshold Voltage vs. Temperature
-75 -50 -25 0 25 50 75 100 125 150
T
J
, Temperature ( °C )
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
V
G
S
(
t
h
)
,
G
a
t
e
t
h
r
e
s
h
o
l
d
V
o
l
t
a
g
e
(
V
)
I
D
= 50μA
I
D
= 250μA
I
D
= 1.0mA
I
D
= 1.0A
1E-006 1E-005 0.0001 0.001 0.01 0.1
t
1
, Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
T
h
e
r
m
a
l
R
e
s
p
o
n
s
e
(
Z
t
h
J
C
)
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.2 0.4 0.6 0.8 1.0 1.2 1.4
V
SD
, Source-to-Drain Voltage (V)
1.0
10
100
1000
I
S
D
,
R
e
v
e
r
s
e
D
r
a
i
n
C
u
r
r
e
n
t
(
A
)
T
J
= 25°C
T
J
= 150°C
V
GS
= 0V
25 50 75 100 125 150
T
C
, Case Temperature (°C)
0
20
40
60
80
100
120
I
D
,
D
r
a
i
n
C
u
r
r
e
n
t
(
A
)
Limited By Source
Bonding Technology
0.1 1 10 100
V
DS
, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
10000
I
D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
Tc = 25°C
Tj = 150°C
Single Pulse
OPERATION IN THIS AREA
LIMITED BY R
DS
(on)
100μsec
1msec
10msec
DC
Limited By Source
Bonding Technology
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IRFH8318PbF
Fig 13. Maximum Avalanche Energy vs. Drain Current
Fig 12. On-Resistance vs. Gate Voltage
Fig 14b. Unclamped Inductive Waveforms
Fig 14a. Unclamped Inductive Test Circuit
t
p
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
V
DS
+
-
V
DD
DRIVER
A
15V
20V
Fig 15a. Switching Time Test Circuit
Fig 15b. Switching Time Waveforms
V
GS
V
DS
90%
10%
t
d(on)
t
d(off)
t
r
t
f
V
DS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1
R
D
V
GS
R
G
D.U.T.
10V
+
-
V
DD
V
GS
0 5 10 15 20
V
GS,
Gate -to -Source Voltage (V)
2
4
6
8
10
R
D
S
(
o
n
)
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
O
n
R
e
s
i
s
t
a
n
c
e
(
m
Ω
)
I
D
= 20A
T
J
= 25°C
T
J
= 125°C
25 50 75 100 125 150
Starting T
J
, Junction Temperature (°C)
0
100
200
300
400
500
600
700
E
A
S
,
S
i
n
g
l
e
P
u
l
s
e
A
v
a
l
a
n
c
h
e
E
n
e
r
g
y
(
m
J
)
I
D
TOP 5.6A
8.6A
BOTTOM 20A
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IRFH8318PbF
Fig 16. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET
®
Power MOSFETs
Fig 17. Gate Charge Test Circuit
Fig 18. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1
Qgs2 Qgd Qgodr
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P. W .
Period
* V
GS
= 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
R
G
V
DD
dv/dt controlled by R
G
Driver same type as D.U.T.
I
SD
controlled by Duty Factor "D"
D.U.T. - Device Under Test
D.U.T
1K
VCC
DUT
0
L
S

IRFH8318TRPBF

Mfr. #:
Manufacturer:
Infineon / IR
Description:
MOSFET 30V 1 N-CH HEXFET 3.1mOhms 41nC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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