SMP18FSZ

REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Octal Sample-and-Hold
with Multiplexed Input
SMP18
FUNCTIONAL BLOCK DIAGRAM
SW
SW
SW
SW
SW
SW
SW
SW
1 OF 8 DECODER
691011
3
13
16
8
14
15
12
7
1
2
4
5
DGND
V
DD
CH
0
OUT
CH
1
OUT
CH
2
OUT
CH
3
OUT
CH
4
OUT
CH
5
OUT
CH
6
OUT
CH
7
OUT
V
SS
HOLD CAPS
(INTERNAL)
SMP18
INPUT
(LSB)
A
B
(MSB)
C
INH
FEATURES
High Speed Version of SMP08
Internal Hold Capacitors
Low Droop Rate
TTL/CMOS Compatible Logic Inputs
Single or Dual Supply Operation
Break-Before-Make Channel Addressing
Compatible With CD4051 Pinout
Low Cost
APPLICATIONS
Multiple Path Timing Deskew for A.T.E.
Memory Programmers
Mass Flow/Process Control Systems
Multichannel Data Acquisition Systems
Robotics and Control Systems
Medical and Analytical Instrumentation
Event Analysis
Stage Lighting Control
GENERAL DESCRIPTION
The SMP18 is a monolithic octal sample-and-hold; it has eight
internal buffer amplifiers, input multiplexer, and internal hold
capacitors. It is manufactured in an advanced oxide isolated
CMOS technology to obtain high accuracy, low droop rate, and
fast acquisition time. The SMP18 has a typical linearity error of
only 0.01% and can accurately acquire a 10-bit input signal to
±1/2 LSB in less than 2.5 microseconds. The SMP18’s output
swing includes the negative supply in both single and dual sup-
ply operation.
The SMP18 was specifically designed for systems that use a
calibration cycle to adjust a multiple of system parameters. The
low cost and high level of integration make the SMP18 ideal for
calibration requirements that have previously required an ASIC,
or high cost multiple D/A converters.
The SMP18 is also ideally suited for a wide variety of sample-
and-hold applications including amplifier offset or VCA gain ad-
justments. One or more SMP18s can be used with single or
multiple DACs to provide multiple set points within a system.
The SMP18 offers significant cost and size reduction over
discrete designs. It is available in a 16-pin plastic DIP, a
narrow body SO-16 surface-mount SOIC package or the thin
TSSOP-16 package. The SMP18 is a higher speed direct
replacement for the SMP08.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703 © Analog Devices, Inc., 1996
SMP18* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
DOCUMENTATION
Application Notes
AN-204: Applications of the SMP04 and the SMP08/18
Quad and Octal Sample-and-Hold Amplifiers
Data Sheet
SMP18: Octal Sample-and-Hold with Multiplexed Input
Data Sheet
DESIGN RESOURCES
SMP18 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
View all SMP18 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
ELECTRICAL CHARACTERISTICS
P
arameter Symbol Conditions Min Typ Max Units
Linearity Error –3 V V
IN
+3 V 0.01 %
Buffer Offset Voltage V
OS
T
A
= +25°C, V
IN
= 0 V 2.5 10 mV
–40°C T
A
+85°C, V
IN
= 0 V 3.5 20 mV
Hold Step V
HS
V
IN
= 0 V, T
A
= +25°C to +85°C 46mV
V
IN
= 0 V, T
A
= –40°C8mV
Droop Rate V
CH
/tT
A
= +25°C, V
IN
= 0 V 2 40 mV/s
Output Source Current I
SOURCE
V
IN
= 0 V
1
1.2 mA
Output Sink Current I
SINK
V
IN
= 0 V
1
0.5 mA
Output Voltage Range R
L
= 20 k –3.0 +3.0 V
LOGIC CHARACTERISTICS
Logic Input High Voltage V
INH
2.4 V
Logic Input Low Voltage V
INL
0.8 V
Logic Input Current I
IN
V
IN
= 2.4 V 0.5 1 µA
DYNAMIC PERFORMANCE
2
Acquisition Time
3
t
AQ
T
A
= +25°C, –3 V to +3 V to 0.1% 3.5 µs
Hold Mode Settling Time t
H
To ±1 mV of Final Value 1 µs
Channel Select Time t
CH
90 ns
Channel Deselect Time t
DCS
45 ns
Inhibit Recovery Time t
IR
90 ns
Slew Rate SR 6 V/µs
Capacitive Load Stability <30% Overshoot 500 pF
Analog Crosstalk –3 V to +3 V Step –72 dB
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio PSRR V
SS
= ±5 V to ±6 V 60 75 dB
Supply Current I
DD
T
A
= +25°C 5.5 7.5 mA
–40°C T
A
+85°C
7.5 9.5 mA
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ Max Limits
Linearity Error 60 mV V
IN
10 V 0.01 %
Buffer Offset Voltage V
OS
T
A
= +25°C, V
IN
= 6 V 2.5 10 mV
–40°C T
A
+85°C, V
IN
= 6 V 3.5 20 mV
Hold Step V
HS
V
IN
= 6 V, T
A
= +25°C to +85°C 46mV
V
IN
= 6 V, T
A
= –40°C8mV
Droop Rate V
CH
/tT
A
= +25°C, V
IN
= 6 V 2 40 mV/s
Output Source Current I
SOURCE
V
IN
= 6 V
1
1.2 mA
Output Sink Current I
SINK
V
IN
= 6 V
1
0.5 mA
Output Voltage Range R
L
= 20 k 0.06 10.0 V
R
L
= 10 k 0.06 9.5 V
LOGIC CHARACTERISTICS
Logic Input High Voltage V
INH
2.4 V
Logic Input Low Voltage V
INL
0.8 V
Logic Input Current I
IN
V
IN
= 2.4 V 0.5 1 µA
DYNAMIC PERFORMANCE
2
Acquisition Time
3
t
AQ
T
A
= +25°C, 0 to 10 V to 0.1% 2.5 3.25 µs
Hold Mode Settling Time t
H
To ±1 mV of Final Value 1 µs
Channel Select Time t
CH
90 ns
Channel Deselect Time t
DCS
45 ns
Inhibit Recovery Time t
IR
90 ns
Slew Rate
4
SR 7 V/µs
Capacitive Load Stability <30% Overshoot 500 pF
Analog Crosstalk 0 V to 10 V Step –72 dB
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio PSRR 10.8 V V
DD
13.2 V 60 75 dB
Supply Current I
DD
T
A
= +25°C 6.0 8.0 mA
–40°C T
A
+85°C 8.0 10.0 mA
NOTES
1
Outputs are capable of sinking and sourcing over 10 mA but offset is guaranteed at specified load levels.
2
All input control signals are specified with t
r
= t
f
= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
3
This parameter is guaranteed without test.
4
Slew rate is measured in the sample mode with a 0 to 10 V step from 20% to 80%.
Specifications subject to change without notice.
REV. C
–2–
SMP18–SPECIFICATIONS
(@ V
DD
= +5 V, V
SS
= –5 V, DGND = 0 V, R
L
= No Load, T
A
= –408C to +858C for SMP18F,
unless otherwise noted)
(@ V
DD
= +12 V, V
SS
= 0 V, DGND = 0 V, R
L
= No Load, T
A
= –408C to +858C for SMP18F,
unless otherwise noted)

SMP18FSZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Sample & Hold Amplifiers OCTAL S/H WITH MUX INPUT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union