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95V847AGLFT

P1-P3P4-P6P7-P9
7
ICS95V847
0718E—11/24/08
(N is a large number of samples)
t
( ) n+1
t
()n
t
()
=
1
n=
N
t
()n
N
CLK_INC
CLK_INT
FB_INC
FB_INT
t
(SK_O)
Y
#
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y
X
Parameter Measurement Information
Figure 4. Static Phase Offset
Figure 5. Output
Skew
1
f
O
t
=
t
-
(jit_per) C(n)
1
f
O
Figure 6. Period Jitter
8
ICS95V847
0718E—11/24/08
Clock Inputs
and Outputs
80%
20%
80%
20%
Rise t
sl
Fall t
sl
V
ID
,V
OD
Figure 8. Input and Output Slew Rates
Parameter Measurement
Information
t
(hper_n)
t
(hper_n+1)
1
f
o
Y , FB_OUTC
X
Y , FB_OUTT
X
Figure 7. Half-Period Jitter
t
=-
(jit_Hper)
t
(jit_Hper_n)
1
2xf
O
9
ICS95V847
0718E—11/24/08
Ordering Information
95V847yGLF-T
4.40 mm. Body, 0.65 mm. pitch TSSOP
(173 mil)
(0.0256 Inch)
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1
E
α
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
c
L
aaa
C
MIN MAX MIN MAX
A--1.20--.047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.19 0.30 .007 .012
c 0.09 0.20 .0035 .008
D
E
E1 4.30 4.50 .169 .177
e
L 0.45 0.75 .018 .030
N
a0°8°0°8°
aaa -- 0.10 -- .004
VARIATIONS
MIN MAX MIN MAX
24 7.70 7.90 .303 .311
10-0035
N
D mm. D (inch)
Reference Doc.: JEDEC Publication 95, MO-153
0.65 BASIC 0.0256 BASIC
SEE VARIATIONS SEE VARIATIONS
SEE VARIATIONS SEE VARIATIONS
6.40 BASIC 0.252 BASIC
SYMBOL
In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
Example:
XXXX y G LF- T
Designation for tape and reel packaging
Annealed Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
P1-P3P4-P6P7-P9

95V847AGLFT

Mfr. #:
Buy 95V847AGLFT
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 1:5, 2.5V Phase-Lock Loop Clock Driver
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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