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LTC1093CN#PBF

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LTC1091/LTC1092
LTC1093/LTC1094
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Interfacing to the Parallel Port of the
Intel 8051 Family
The Intel 8051 has been chosen to demonstrate the
interface between the LTC1091 and parallel port micro-
processors. Normally, the CS, SCLK and D
IN
signals
would be generated on three port lines and the D
OUT
signal
read on a 4th port line. This works very well. However, we
will demonstrate here an interface with the D
IN
and D
OUT
of the LTC1091 tied together as described in section 4.
This saves one wire.
The 8051 first sends the start bit and MUX address to the
LTC1091 over the data line connected to P1.2. Then P1.2
is reconfigured as an input (by writing to it a one) and the
8051 reads back the 10-bit A/D result over the same data
line.
1091-4 AI17
LTC1091
CS
CLK
D
OUT
D
IN
ANALOG
INPUTS
P1.4
P1.3
P1.2
8051
MUX ADDRESS
A/D RESULT
B9 B8 B7 B6 B5 B4 B3 B2
D
OUT
from LTC1091 Stored in 8051 RAM
MSB
R2
B1 B0 0 0 0 0 0 0
LSB
R3
LABEL MNEMONIC OPERAND COMMENTS
MOV A, #FFH D
IN
Word for LTC1091
SETB P1.4 Make Sure CS Is High
CLR P1.4 CS Goes Low
MOV R4, #04 Load Counter
LOOP 1 RLC A Rotate D
IN
Bit into Carry
CLR P1.3 SCLK Goes Low
MOV P1.2, C Output D
IN
Bit to LTC1091
SETB P1.3 SCLK Goes High
DJNZ R4, LOOP 1 Next Bit
MOV P1, #04 Bit 2 Becomes an Input
CLR P1.3 SCLK Goes Low
MOV R4, #09 Load Counter
LOOP MOV C, P1.2 Read Data Bit into Carry
RLC A Rotate Data Bit into Acc
SETB P1.3 SCLK Goes High
CLR P1.3 SCLK Goes Low
DJNZ R4, LOOP Next Bit
MOV R2, A Store MSBs in R2
MOV C, P1.2 Read Data Bit into Carry
SETB P1.3 SCLK Goes High
CLR P1.3 SCLK Goes Low
CLR A Clear Acc
RLC A Rotate Data Bit from Carry to Acc
MOV C, P1.2 Read Data Bit into Carry
RRC A Rotate Right into Acc
RRC A Rotate Right into Acc
MOV R3, A Store LSBs in R3
SETB P1.4 CS Goes High
1091/2/3/4 AI18
CLK
START
MSBF
B9
B8 B7
B6
B5 B4 B3
B2
B1 B0
8051 P1.2 RECONFIGURED AS AN
INPUT AFTER THE 4TH RISING CLK
AND BEFORE THE 4TH FALLING CLK
8051 P1.2 OUTPUTS
DATA TO LTC1091
LTC1091 TAKES CONTROL OF DATA LINE
ON 4TH FALLING CLK
SGL/
DIFF
ODD/
SIGN
CS
DATA (D
IN
/D
OUT
)
12
MSBF BIT
LATCHED
INTO LTC1091
3
4
LTC1091 SENDS A/D RESULT
BACK TO 8051 P1.2
20
LTC1091/LTC1092
LTC1093/LTC1094
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Figure 3. Several LTC1094s Sharing One 3-Wire Serial Interface
8 CHANNELS 8 CHANNELS
8 CHANNELS
3
3
33
3-WIRE SERIAL
INTERFACE TO OTHER
PERIPHERALS OR LTC1094s
2
10
OUTPUT PORT
SERIAL DATA
MPU
LTC1091-4 F03
LTC1094
CS
LTC1094
CS
LTC1094
CS
Sharing the Serial Interface
The LTC1094 can share the same 2- or 3-wire serial
interface with other peripheral components or other
LTC1094s (see Figure 3). In this case, the CS signals
decide which LTC1094 is being addressed by the MPU.
ANALOG CONSIDERATIONS
1. Grounding
The LTC1091/LTC1092/LTC1093/LTC1094 should be used
with an analog ground plane and single point grounding
techniques.
The AGND pin (GND on the LTC1091/LTC1092) should be
tied directly to this ground plane.
The DGND pin of the LTC1093/LTC1094 can also be tied
directly to this ground plane because minimal digital noise
is generated within the chip itself.
The V
CC
pin should be bypassed to the ground plane with
a 4.7µF tantalum with leads as short as possible. AV
CC
and
DV
CC
should be tied together on the LTC1094. The V
–
pin
(LTC1093/LTC1094) should be bypassed with a 0.1µF
ceramic disk. For single supply applications, V
–
can be
tied to the ground plane.
It is also recommended that the REF
–
pin and the COM pin
be tied directly to the ground plane. All analog inputs
should be referenced directly to the single point ground.
Digital inputs and outputs should be shielded from and/or
routed away from the reference and analog circuitry.
Figure 4. Example Ground Plane for the LTC1091
Figure 4 shows an example of an ideal LTC1091 ground
plane design for a 2-sided board. Of course, this much
ground plane will not always be possible, but users should
strive to get as close to this ideal as possible.
2. Bypassing
For good performance, V
CC
must be free of noise and
ripple. Any changes in the V
CC
voltage with respect to
analog ground during a conversion cycle can induce
errors or noise in the output code. Because the V
CC
(V
REF
)
pin of the LTC1091 defines the voltage span of the A/D
converter, its bypassing is especially important. V
CC
noise
and ripple can be kept below 1mV by bypassing the V
CC
pin
directly to the analog ground plane with a 4.7µF tantalum
with leads as short as possible. AV
CC
and DV
CC
should be
tied together on the LTC1094. Figures 5 and 6 show the
effects of good and poor V
CC
bypassing.
1
2
3
4
S
S
8
7
6
5
4.7µF
TANTALUM
V
CC
LTC1091-4 F04
21
LTC1091/LTC1092
LTC1093/LTC1094
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3. Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1091/
LTC1092/LTC1093/LTC1094 have capacitive switching
input current spikes. These current spikes settle quickly
and do not cause a problem. However, if large source
resistances are used or if slow settling op amps drive the
inputs, care must be taken to ensure that the transients
caused by the current spikes settle completely before the
conversion begins.
Source Resistance
The analog inputs of the LTC1091/LTC1092/LTC1093/
LTC1094 look like a 60pF capacitor (C
IN
) in series with a
500Ω resistor (R
ON
) as shown in Figure 7.
C
IN
gets
switched between the selected “+” and “–” inputs once
during each conversion cycle. Large external source resis-
tors and capacitances will slow the settling of
the inputs. It
is important that the overall RC time constants be short
enough to allow the analog inputs to completely settle
within the allowed time.
“+” Input Settling
This input capacitor is switched onto the “+” input during
the sample phase (t
SMPL
, see Figure 8). The sample phase
is the 1 1/2 CLK cycles before the conversion starts. The
voltage on the “+” input must settle completely within this
sample time. Minimizing R
SOURCE
+
and C1 will improve
the input settling time. If large “+” input source resistance
must be used, the sample time can be increased by using
a slower CLK frequency. With the minimum possible
sample time of 3µs, R
SOURCE
+
< 2k and C1 < 20pF will
provide adequate settling.
Figure 5. Poor V
CC
Bypassing.
Noise and Ripple Can Cause A/D Errors
10µs/DIV
1091-4 F05
0.5mV/DIV
Figure 6. Good V
CC
Bypassing Keeps
Noise and Ripple on V
CC
Below 1mV
0.5mV/DIV
10µs/DIV
1091-4 F06
3RD CLK↑
R
ON
= 500Ω
4TH CLK↓
C
IN
=
60pF
LTC1091
“+”
INPUT
R
SOURCE
+
V
IN
+
C1
“–”
INPUT
R
SOURCE
–
V
IN
–
C2
LTC091-4 F07
Figure 7. Analog Input Equivalent Circuit
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LTC1093CN#PBF

Mfr. #:
Buy LTC1093CN#PBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 10-Bit Serial I/O ADC w/6CH MUX
Lifecycle:
New from this manufacturer.
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