DATASHEET
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER MK2308-1H
IDT™ / ICS™
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER 1
MK2308-1H REV F 122109
Description
The MK2308-1H is a low phase noise, high-speed PLL
based, 8-output, low skew zero delay buffer. Based on IDT’s
proprietary low jitter Phase Locked Loop (PLL) techniques,
the device provides eight low skew outputs at speeds up to
133 MHz at 3.3 V. The outputs can be generated from the
PLL (for zero delay), or directly from the input (for testing),
and can be set to tri-state mode or to stop at a low level. For
normal operation as a zero delay buffer, any output clock is
tied to the FBIN pin.
IDT manufactures a large variety of clock generators and
buffers.
Features
• Clock outputs from 10 to 133 MHz
• Zero input-output delay
• Eight low skew (<200 ps) outputs
• Device-to-device skew <700 ps
• Full CMOS outputs with 25 mA output drive capability at
TTL levels
• 5 V tolerant FBIN and CLKIN pins
• Tri-state mode for board-level testing
• Advanced, low-power, sub-micron CMOS process
• Operating voltage of 3.3 V
• Industrial temperature range available
• Packaged in 16-pin SOIC and TSSOP packages
• Available in Pb (lead) free package
• Industrial and commercial temp operation
NOTE: EOL for non-green parts to occur on 5/13/10
per PDN U-09-01
Block Diagram
CLKA4
CLKB1
CLKA3
CLKB2
CLKB3
CLKA2
CLKA1
CLKB4
CLKIN
Control
Logic
1
0
S2, S1
2
Clock
Synthesis
PLL
FBIN
Feedback is shown from CLKB4 for
illustration, but may come from any output.
VDD
2
GND
2
