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ADRF5044-EVALZ

P1-P3P4-P6P7-P9P10-P12P13-P14
100 MHz to 30 GHz,
Silicon, SP4T Switch
Data Sheet
ADRF5044
Rev. 0 Document Feedback
Information
furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Ultrawideband frequency range: 100 MHz to 30 GHz
Nonreflective 50 Ω design
Low insertion loss: 2.6 dB at 20 GHz to 30 GHz
High isolation: 43 dB at 20 GHz to 30 GHz
High input linearity
P1dB: 28 dBm typical
IP3: 50 dBm typical
High power handling
24 dBm through path
24 dBm terminated path
No low frequency spurious
0.1 dB settling time (50% V
CTL
to 0.1 dB of final RF output): 37 ns
24-terminal LGA package
APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military radios, radars, and electronic counter measures (ECMs)
Broadband telecommunications systems
FUNCTIONAL BLOCK DIAGRAM
RF2
GND
GND
RF1
GND
GND
RF4
GND
GND
GND
RF3
GND
GND
GND
RFC
GND
GND
GND
V2
V1
VDD
GND
50Ω
VSS
GND
1
2
3
4
5
6
7 8 9 10
11 12
13
14
15
16
17
18
19
20
2122
23
24
DRIVER
50Ω
50Ω50Ω
ADRF5044
16313-001
Figure 1.
GENERAL DESCRIPTION
The ADRF5044 is a general-purpose, single-pole, four-throw
(SP4T) switch manufactured using a silicon process. It comes in
a 24-terminal land grid array (LGA) package and provides high
isolation and low insertion loss from 100 MHz to 30 GHz.
This broadband switch requires dual-supply voltages, +3.3 V and
−3.3 V, a n d p rovides complementary metal-oxide semiconductor
(CMOS)/low voltage transistor-transistor logic (LVTTL) logic-
compatible control.
ADRF5044 Data Sheet
Rev. 0 | Page 2 of 14
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
Power Derating Curves ................................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Interface Schematics..................................................................... 6
Typical Performance Characteristics ..............................................7
Insertion Loss, Return Loss, and Isolation ................................7
Input 0.1 dB and 1 dB Power Compression and Third-Order
Intercept ..........................................................................................9
Theory of Operation ...................................................................... 10
Applications Information .............................................................. 11
Evaluation Board ........................................................................ 11
Probe Matrix Board ................................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
12/2017—Revision 0: Initial Version
Data Sheet ADRF5044
Rev. 0 | Page 3 of 14
SPECIFICATIONS
V
DD
= 3.3 V, V
SS
= −3.3 V, V 1 = 0 V or 3.3 V, V2 = 0 V or 3.3 V, and T
CASE
= 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE 100 30,000 MHz
INSERTION LOSS
Between RFC and RF1 to RF4 (On) (Worst Case) 100 MHz to 10 GHz 1.7 dB
10 GHz to 20 GHz 2.1 dB
20 GHz to 30 GHz 2.6 dB
ISOLATION
Between RFC and RF1 to RF4 (Off ) (Worst Case) 100 MHz to 10 GHz 55 dB
10 GHz to 20 GHz 52 dB
20 GHz to 30 GHz 43 dB
RETURN LOSS
RFC and RF1 to RF4 (On) 100 MHz to 10 GHz 16 dB
10 GHz to 20 GHz 22 dB
20 GHz to 30 GHz 22 dB
RF1 to RF4 (Off) 100 MHz to 10 GHz 24 dB
10 GHz to 20 GHz 24 dB
20 GHz to 30 GHz 16 dB
SWITCHING TIME
Rise and Fall t
RISE
, t
FALL
10% to 90% of radio frequency (RF) output 4 ns
On and Off t
ON
, t
OFF
50% V
CTL
to 90% of RF output 19 ns
Settling
0.1 dB 50% V
CTL
to 0.1 dB of final RF output 37 ns
0.05 dB 50% V
CTL
to 0.05 dB of final RF output 50 ns
INPUT LINEARITY
Power Compression
0.1 dB P0.1dB 26 dBm
1 dB P1dB 28 dBm
Third-Order Intercept
IP3
Δf = 1 MHz
50
dBm
SUPPLY CURRENT VDD, VSS pins
Positive I
DD
Typical at V
CTL
= 0 V or 3.3 V, maximum at
V
CTL
= 0.8 V or 1.4 V
12 20 µA
Negative I
SS
Typical at V
CTL
= 0 V or 3.3 V, maximum at
V
CTL
= 0.8 V or 1.4 V
110 130 µA
DIGITAL CONTROL INPUTS V1, V2 pins
Voltage
Low V
INL
0 0.8 V
High V
INH
1.2 3.3 V
Current
Low and High I
INL,
I
INH
<1 µA
RECOMMENDED OPERATING CONDITONS
Supply Voltage
Positive V
DD
3.15 3.45 V
Negative V
SS
−3.45 −3.15 V
Digital Control Voltage V
CTL
0 V
DD
V
P1-P3P4-P6P7-P9P10-P12P13-P14

ADRF5044-EVALZ

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Manufacturer:
Analog Devices Inc.
Description:
RF Development Tools Eval Board ADRF5044
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