MAX8552
High-Speed, Wide-Input,
Single-Phase MOSFET Driver
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Detailed Description
The MAX8552 single-phase gate driver, along with the
MAX8524/MAX8525 multiphase controllers, provide
flexible one- to eight-phase CPU core-voltage supplies.
The 1.0Ω/1.3Ω driver resistance allows up to 30A out-
put current per phase. Each MOSFET driver in the
MAX8552 is capable of driving 3000pF capacitive
loads with only 12ns propagation delay and 11ns (typ)
rise and fall times, allowing operation up to 1.2MHz per
phase. Adaptive dead time controls MOSFET turn-on,
and user-programmable dead time provides additional
flexibility for high-side MOSFET turn-on. This maximizes
converter efficiency, while allowing operation with a vari-
ety of MOSFETs and PWM-controller ICs. An undervolt-
age-lockout circuit allows proper power-on sequencing.
The PWM signal input is both TTL and CMOS compati-
ble. An enable input allows total driver shutdown
(<0.1µA typ) for power-sensitive portable applications.
MOSFET Gate Drivers (DH, DL)
The high-side driver (DH) has a 1.3Ω (typ) sourcing
resistance and 0.7Ω sinking resistance, resulting in 4A
peak sourcing current and 7A peak sinking current with
a 5V supply voltage. The low-side driver (DL) has a typ-
ical 1.0Ω sourcing resistance and 0.5Ω sinking resis-
tance, yielding 5A peak sourcing current and 10A peak
sinking current. This reduces switching losses, making
the MAX8552 ideal for both high-frequency and high-
output-current applications.
Shoot-Through Protection and
Programmable Delay (t
DLY
)
The MAX8552 incorporates adaptive shoot-through pro-
tection for the switching transition after the high-side
MOSFET turns off and before the low-side MOSFET turns
on and vice versa. The low-side driver turns on only
when the LX voltage falls below 2.4V. Furthermore, the
delay time between the low-side MOSFET turn-off and
high-side MOSFET turn-on can be adjusted by selecting
the value of R1 (see the R
DLY
Selection section).
Undervoltage Lockout
When V
CC
is below the UVLO threshold (3.5V typ), DH
and DL are held low. Once V
CC
is above the UVLO
threshold and while PWM is low, DL is driven high and
DH is driven low. This prevents the output of the con-
verter from rising before a valid PWM signal is applied.
EN
When EN is low, the MAX8552 is in shutdown mode
and the total input current is reduced to less than 1µA
for power-sensitive applications. In shutdown mode,
both DH and DL are held low. When EN goes high, the
MAX8552 becomes active.
Applications Information
Decoupling of V
CC
V
CC
provides the supply voltage for the internal logic
circuits. Bypass V
CC
with a 2.2µF or larger capacitor to
PGND and a 0.47µF or larger capacitor to GND to limit
noise to the internal circuitry. Connect these bypass
capacitors as close to the IC as possible.
Boost Flying-Capacitor Selection
The MAX8552 uses a bootstrap circuit to generate the
necessary drive voltage (V
DH
) to fully enhance the
high-side N-MOSFET. The selected high-side MOSFET
determines appropriate boost capacitance values (C6
in the Typical Application Circuit, Figure 1), according
to the following equation:
C
BST
= Q
GATE
/ ∆V
BST
where Q
GATE
is the total gate charge of the high-side
MOSFET and ∆V
BST
is the voltage variation allowed on
the high-side MOSFET driver. Choose ∆V
BST
= 0.1V to
0.2V when determining C
BST
. The boost flying-capaci-
tor should be a low-equivalent series resistance (ESR)
ceramic capacitor.
R
DLY
Selection
Connect DLY to V
CC
to disable the programmable delay
function and default to the adaptive delay time. To pro-
gram a longer specific delay time between the low-side
MOSFET driver turn-off and the high-side MOSFET turn-
on, connect a delay resistor, R
DLY
, between DLY and
GND (R1 in the Typical Application Circuit, Figure 1).
See the Typical Operating Characteristics to select R
DLY
.
Avoiding dV/dt Turning on
the Low-Side MOSFET
At high input voltages, fast turn-on of the high-side MOSFET
can momentarily turn on the low-side MOSFET due to the
high dV/dt appearing at the drain of the low-side MOSFET.
The high dV/dt causes a current flow through the Miller
capacitance (C
RSS
) and the input capacitance (C
ISS
)
of the low-side MOSFET. Improper selection of the low-
side MOSFET that results in a high ratio of C
RSS
/C
ISS
makes the problem more severe. To avoid this prob-
lem, minimize the ratio of C
RSS
/C
ISS
when selecting the
low-side MOSFET. Adding a 1Ω resistor between BST
and C
BST
can slow the high-side MOSFET turn-on.
Similarly, adding a small capacitor from the gate to the
source of the high-side MOSFET has the same effect.
However, both methods work at the expense of
increased switching losses.
