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74LVC163PW,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
74LVC163 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 20 November 2012 9 of 20
NXP Semiconductors
74LVC163
Presettable synchronous 4-bit binary counter; synchronous reset
[1] Typical values are measured at T
amb
=25C and V
CC
= 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
N = number of inputs switching
(C
L
V
CC
2
f
o
) = sum of outputs
t
su
set-up time Dn to CP; see Figure 12
V
CC
= 1.65 V to 1.95 V 5.0 - - 5.0 - ns
V
CC
= 2.3 V to 2.7 V 4.0 - - 4.0 - ns
V
CC
= 2.7 V 3.0 - - 3.0 - ns
V
CC
= 3.0 V to 3.6 V 2.5 1.0 - 2.5 - ns
MR
, PE to CP; see Figure 12
V
CC
= 1.65 V to 1.95 V 4.5 - - 4.5 - ns
V
CC
= 2.3 V to 2.7 V 4.0 - - 4.0 - ns
V
CC
= 2.7 V 3.5 - - 3.5 - ns
V
CC
= 3.0 V to 3.6 V 3.0 1.2 - 3.0 - ns
CEP, CET to CP; see Figure 13
V
CC
= 1.65 V to 1.95 V 8.5 - - 8.5 - ns
V
CC
= 2.3 V to 2.7 V 6.5 - - 6.5 - ns
V
CC
= 2.7 V 5.5 - - 5.5 - ns
V
CC
= 3.0 V to 3.6 V 5.0 2.1 - 5.0 - ns
t
h
hold time Dn, PE, CEP, CET to CP; see
Figure 12 and 13
V
CC
= 1.65 V to 1.95 V 2.0 - - 2.0 - ns
V
CC
= 2.3 V to 2.7 V 2.0 - - 2.0 - ns
V
CC
= 2.7 V 0.0 - - 0.0 - ns
V
CC
= 3.0 V to 3.6 V 0.5 0.0 - 0.5 - ns
f
max
maximum
frequency
see Figure 9
V
CC
= 1.65 V to 1.95 V 100 - - 80 - ns
V
CC
= 2.3 V to 2.7 V 125 - - 100 - ns
V
CC
= 2.7 V 150 - - 120 - MHz
V
CC
= 3.0 V to 3.6 V 150 200 - 120 - MHz
t
sk(o)
output skew time V
CC
= 3.0 V to 3.6 V
[3]
- - 1.0 - 1.5 ns
C
PD
power dissipation
capacitance
per input; V
I
= GND to V
CC
[4]
V
CC
= 1.65 V to 1.95 V - 9.8 - - - pF
V
CC
= 2.3 V to 2.7 V - 13.4 - - - pF
V
CC
= 3.0 V to 3.6 V - 16.6 - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 14.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
74LVC163 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 20 November 2012 10 of 20
NXP Semiconductors
74LVC163
Presettable synchronous 4-bit binary counter; synchronous reset
11. AC waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 9. Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, and the maximum frequency
mgu762
CP
input
Qn, TC
output
t
PHL
t
PLH
t
W
V
M
V
OH
V
I
GND
V
OL
V
M
1/f
max
V
M
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 10. Input (CET) to output (TC) propagation delays
mgu763
CET input
TC output
t
PLH
t
PHL
GND
V
I
V
M
V
M
V
M
V
M
V
OH
V
OL
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 11. Master reset (MR) pulse width, the master reset to output (Qn, TC) propagation delays and the master
reset to clock (CP) removal times
mgu764
t
h
t
su
t
h
t
su
V
M
V
M
V
M
V
I
GND
V
I
GND
CP input
MR input
74LVC163 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 20 November 2012 11 of 20
NXP Semiconductors
74LVC163
Presettable synchronous 4-bit binary counter; synchronous reset
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 12. Set-up and hold times for the input (Dn) and parallel enable input (PE)
mgu765
t
h
t
su
t
h
t
su
t
h
t
su
t
h
t
su
V
M
V
M
V
M
V
M
V
M
V
M
V
I
GND
Dn input
V
I
GND
CP input
V
I
GND
PE input
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 13. CEP and CET set-up and hold times
mgu766
t
h
t
su
t
h
t
su
V
M
V
M
V
M
V
M
V
I
GND
V
I
GND
CP input
CEP, CET input
Table 8. Measurement points
Supply voltage Input Output
V
CC
V
I
V
M
V
M
1.2 V V
CC
0.5 V
CC
0.5 V
CC
1.65 V to 1.95 V V
CC
0.5 V
CC
0.5 V
CC
2.3 V to 2.7 V V
CC
0.5 V
CC
0.5 V
CC
2.7 V 2.7 V 1.5 V 1.5 V
3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

74LVC163PW,118

Mfr. #:
Buy 74LVC163PW,118
Manufacturer:
Nexperia
Description:
Counter ICs 4-BIT SYNC BIN CNTR
Lifecycle:
New from this manufacturer.
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