74LVC163 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 20 November 2012 12 of 20
NXP Semiconductors
74LVC163
Presettable synchronous 4-bit binary counter; synchronous reset
Test data is given in Table 9.
Definitions for test circuit:
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
Fig 14. Load circuitry for switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aaf615
V
CC
V
I
V
O
DUT
C
L
R
T
R
L
PULSE
GENERATOR
Table 9. Test data
Supply voltage Input Load
V
I
t
r
, t
f
C
L
R
L
1.2 V V
CC
2 ns 30 pF 1 k
1.65 V to 1.95 V V
CC
2 ns 30 pF 1 k
2.3 V to 2.7 V V
CC
2 ns 30 pF 500
2.7V 2.7V 2.5 ns 50 pF 500
3.0Vto3.6V 2.7V 2.5 ns 50 pF 500
