74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 12 of 22
NXP Semiconductors
74HC191
Presettable synchronous 4-bit binary up/down counter
Measurement points are given in Table 9.
Logic levels V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 11. The clock and count enable inputs (CP, CE) to ripple clock output (RC) propagation delays
&(LQSXW
9
2+
9
2/
9
0
5&RXWSXW
Measurement points are given in Table 9.
Logic levels V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 12. The input (Dn) to output (Qn) propagation delays
9
0
W
3+/
W
3/+
,
*1'
9
2+
9
2/
9
0
Measurement points are given in Table 9.
Logic levels V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 13. The parallel load input (PL) to output (Qn) propagation delays
9
0
9
0
O
9
O
*1'
/LQSXW
*1'
9
2+
9
2/
W
3/+
W
3+/