ADC1003S040TS/C1,1 Datasheet ADC1003S030TS/C1,1, ADC1003S040TS/C1,1, ADC1003S050TS/C1,1 | P10-P12

Product data sheet Rev. 03 — 2 July 2012 10 of 19

Integrated Design Technology

ADC1003S030/040/050

Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage

regulator

[7] Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental

period. The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to

signal-to-noise ratio: SINAD = ENOB  6.02 + 1.76 dB.

[8] Intermodulation measured relative to either tone with analog inp

ut frequencies of 4.43 MHz and 4.53 MHz. The two input signals have

the same amplitude and the total amplitude of both signals provides full-scale to the converter.

[9] Measurement carried out using video analyzer VM700A, where the video analog sig

nal is reconstructed through a digital-to-analog

converter.

[10] Output data acquisition: the output data is available af

ter the maximum delay time of t

d(o)

. For the 50 MHz version it is recommended to

have the lowest possible output load.

014aaa325

lad

code 1023

code 0

Fig 3. Explanation of Table 6 Table note 3

11. Additional information relating to Table 6

Table 7. Output coding and input voltage (typical values; referenced to AGND)

Code V

i(a)(p-p)

(V)

IR Binary outputs D9 to D0 Two’s complement

outputs D9 to D0

Underflow < 1.455 0 00 0000 0000 10 0000 0000

0 1.455 1 00 0000 0000 10 0000 0000

1 - 1 00 0000 0001 10 0000 0001

 -   

511 2.43  01 1111 1111 11 1111 1111

 -   

1022 - 11 11 1111 1110 01 1111 1110

1023 3.405 1 11 1111 1111 01 1111 1111

Overflow > 3.405 0 11 1111 1111 01 1111 1111

Product data sheet Rev. 03 — 2 July 2012 11 of 19

Integrated Design Technology

ADC1003S030/040/050

Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage

regulator

Table 8. Mode selection

TC OE D9 to D0 IR

X 1 high impedance high impedance

0 0 active; two’s complement active

1 0 active; binary active

014aaa326

CLK

DATA

N − 2

DATA

D0 to D9

DATA

N − 1

DATA

N + 1

sample N + 2sample N + 1

CCO

sample N

sample N + 2

sample N + 1sample N

w(clk)H

w(clk)L

d(s)

d(o)

h(o)

50%

0 V

CCO

50%

0 V

Fig 4. Timing diagram

Product data sheet Rev. 03 — 2 July 2012 12 of 19

Integrated Design Technology

ADC1003S030/040/050

Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage

regulator

LOW

HIGH

LOW

ADC1003S050

CCD

output

data

output

data

10 %

50 %

90 %

50 %

dLZ

dZL

dHZ

dZH

15 pF

3.3 kΩ

TEST

CCD

dLZ

CCD

dZL

DGND

dZH

dHZ

DGND

014aaa334

CCD

frequency on pin OE = 100 kHz

Fig 5. Timing diagram and test conditions of 3-state output delay time.

014aaa327

code 1023

code 0

50%

CLK

s(LH)

s(HL)

50% 50%

2 ns 2 ns

0.5 ns 0.5 ns

Fig 6. Analog input settling-time diagram

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

ADC1003S040TS/C1,1

Mfr. #:

Buy ADC1003S040TS/C1,1

Manufacturer:

Description:

IC ADC 10BIT 28SSOP

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

ADC1003S040TS/C1,1

ADC1003S040TS/C1,1

Products related to this Datasheet