ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 15 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
V
CCD
CLK
1.5 V
DGND
014aaa324
Fig 13. CLK input
12. Application information
12.1 Application diagram
ADC1003S050
CLK
V
CCD1
TC
DGND1
V
CCA
IR
AGND
D9
DEC
D8
RB
(1)
D7
RM
(1)
D6
VI
D5
RT
(1)
D4
OE
D3
V
CCD2
D2
DGND2
D1
V
CCO
D0
OGND
n.c.
(2)
014aaa322
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
18
17
20
19
22
21
24
23
26
25
28
27
100 nF
4.7 nF
1 nF
1 nF
100 nF
100 nF
100 nF
100 nF
(3)
(3)
(3)
(3)
AGND
AGND
AGND
AGND
The analog and digital supplies should be separated and well decoupled.
A user manual is available that describes the demonstration board that uses the ADC1003S030/040/050 family in an
application environment.
(1) RB, RM and RT are decoupled to AGND.
(2) Pin 15 may be connected to DGND in or
der to prevent noise influence.
(3) Decoupling capacitor for supplies: must be placed close to the de
vice.
Fig 14. Application diagram
