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Memory/Operational Register Description
Memory/Register Map
The ISL6295 internal structure is accessible on a strict
memory mapped basis. The only action directly taken by the
ISL6295 in response to an SMBus command is to read or
write registers, SRAM, or EEPROM locations. Any actions
taken by ISL6295 happen as a result of values written to
internal control registers.
Addressing in ISL6295 consists of 10 bits plus two bank
select bits. Therefore, there are a total of 4K byte locations
that are addressable within the ISL6295, organized as 4
banks of 1024 locations each. Bank 0 is dedicated for the
EEPROM. Bank 1 contains the general-purpose SRAM and
the data, status and control registers. Bank 2 contains test
registers, and Bank 3 is reserved.
Table 1 describes the ISL6295 memory map. The notation is
y:0xzzz where y is the bank number and zzz is the register
address in HEX.
EEPROM
The 256 byte EEPROM is located in bank 0 and occupies
address 0:0x000 to 0:0x0FF. The EEPROM can be read
using Byte or Block transfer modes, but can only be written a
byte at a time. Writing the EEPROM takes approximately
4ms/byte. An EEPROM write cycle command from the
SMBus is immediately acknowledged by the ISL6295 if no
other EEPROM write cycles are in progress. If an EEPROM
read or write cycle is attempted while a previous request to
write is in progress, a negative Acknowledge will be returned
until the previous write cycle is completed.
A read or write to a register or SRAM location will not be
affected by an EEPROM write cycle in progress.
FIGURE 8. ISL6295 SMBus READ TRANSACTION
SMBus Address
0
7 0
S
BT AH A
7
1 0
X
6 4
Bank
3 2
Address Low
7 0
# of Bytes (only if BT = 1)
7 0
SMBus Address 1
7 1 0
RS
A
A
A
A
Last Read Data Byte
7
0
A/A
PEC (optional)
7 0
A P Master controls SDA
ISL6295 controls SDA
Legend:
S
- Start
P
-
Stop
RS
- Repeated start
A
-
Acknowdedge
A
- Negative Acknowledge (terminates transaction)
BT
- Block mode indicator bit
Bank
- Controls selection of bank
:
00: EEPROM
01: RAM / Registers
10: Test Mode Registers
11: Reserved
AH
- High order address bits (2)
Address low
- Low order address bits (8)
(Additional data bytes if BT =1)
1
7 0
PEC
- Packet Error Code
ISL6295
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General Purpose SRAM
32 bytes of General Purpose SRAM are provided as
temporary storage and is located in Bank 1 at 1:0x000
through 1:0x01F. The RAM may be read or written using
either the Byte or Block transfer modes.
Operational Registers
The following is a detailed description of all registers within
the ISL6295 including all control, status and result bits, and
fields that are contained therein.
DCA - DISCHARGE COUNT ACCUMULATOR
The DCA is a 32-bit register that holds the total accumulated
current discharged from the battery. While current
accumulation is enabled, the DCA is updated every 0.5s by
adding the magnitude of the latest current conversion result
to the previous accumulated value as long as the sign bit of
the lres register is ‘1’, indicating a discharge condition. When
the sign bit is ‘0’, no accumulation is performed by the DCA.
The DCA register will rollover if it is allowed be updated
beyond 0xFFFFFFFF, so proper register maintenance by the
host system is necessary. The DCA register may be cleared
by setting the "CLR0" bit in the ACCclr register.
DTC - DISCHARGE TIME COUNT REGISTER
The DTC records the length of time that the battery is in a
discharge condition. This register is incremented at a rate of
2Hz for as long as current accumulation is enabled and the
sign bit of the Ires register returns a ‘1’ following a current
conversion.
Time accumulation in the DTC register is not expected to
rollover over the life of the battery pack. If desired, the DTC
register may be cleared by setting the “CLR1” bit in the
ACCclr register.
CCA - CHARGE COUNT ACCUMULATOR
The CCA is a 32-bit register that holds the total accumulated
charging current delivered to the battery. While current
accumulation is enabled, the CCA is updated every 0.5s by
adding the magnitude of the latest current conversion result
to the previous accumulated value as long as the sign bit of
the lres register is ‘0’, indicating a charge condition. When
the sign bit is ‘1’, no accumulation is performed by the CCA.
The CCA register will rollover if it is allowed to be updated
beyond 0xFFFFFFFF, so proper register maintenance by the
host system is necessary. The CCA register may be cleared
by setting the "CLR2" bit in the ACCclr register.
CTC - CHARGE TIME COUNT REGISTER
The CTC records the length of time that the battery is in a
charge condition. This register is incremented at a rate of
2Hz for as long as current accumulation is enabled and the
sign bit of the Ires register returns a ‘0’ following a current
conversion.
Time accumulation in the CTC register is not expected to
rollover over the life of the battery pack. If desired, the CTC
register may be cleared by setting the “CLR3” bit in the
ACCclr register.
TA - TEMPERATURE ACCUMULATOR
TA is the accumulated 32-bit value of temperature
measurements from the internal or external temperature
sensor. TA is updated by the Itres or Etres register. Selection
of the internal temperature sensor or external thermistor for
temperature accumulation is made through the “tsel” bit in
the AccumCtrl register.
The TA register will rollover if it is allowed be updated
beyond 0xFFFFFFFF, so proper register maintenance by the
host system is necessary. The TA register may be cleared by
setting the "CLR4" bit in the ACCclr register.
TAT - TEMPERATURE TIME COUNT REGISTER
The TAT register records the length of time that the ISL6295
is sensing temperature and accumulating the value in
register TA. TAT is incremented at a rate of 2Hz for as long
as temperature accumulation is enabled.
Time accumulation in the TAT register is not expected to
rollover over the life of the battery pack. If desired, the TAT
register may be cleared by setting the “CLR5” bit in the
ACCclr register.
ISL6295
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TABLE 1. ISL6295 MEMORY MAP
FUNCTION BYTE 3 BYTE 2 BYTE 1 BYTE 0
BANK:ADDRESS
(BYTE 0)
EEPROM
↓↓↓ Battery Pack Information (unassigned) ↓↓↓ 0:0x000
// // //
↑↑↑ Battery Pack Information (unassigned) ↑↑↑ 0:0x01C
↓↓↓ Operational Registers Initialization Values ↓↓↓ 0:0x020
// // //
↑↑↑ Operational Registers Initialization Values ↑↑↑ 0:0x078
0:0x07C
Cal / Set-up Register 1 Initialization Values 0:0x080
Cal / Set-up Register 2 Initialization Values 0:0x084
↓↓↓ Cell Look-up Tables (unassigned) ↓↓↓ 0:0x088
// // //
↑↑↑ Cell Look-up Tables (unassigned) ↑↑↑ 0:0x0FC
General Purpose
1:0x000
SRAM
// // //
1:0x01C
Operational
Registers:
Accumulators,
Timers, A/D Registers
and Mode Control
DCA 1:0x020
DTC 1:0x024
CCA 1:0x028
CTC 1:0x02C
TA 1:0x030
TAT 1:0x034
GPADA 1:0x038
GPADT 1:0x03C
ADconfig Ictrl (ADc0) Ires (ADr0) 1:0x040
Reserved
0x00h
ITctrl (ADc1) ITres (ADr1) 1:0x044
ETctrl (ADc2) Etres (ADr2) 1:0x048
VPctrl (ADc3) VPres (ADr3) 1:0x04C
GPIOctrl Reserved Reserved 1:0x050
Reserved
0x00h
GPADctrl (ADc5) GPADres (ADr5) 1:0x054
OFFSctrl (ADc6) OFFSres (ADr6) 1:0x058
AUXctrl (ADc7) AUXres (ADr7) 1:0x05C
ACCctrl ACCclr I+trip 1:0x060
ISL6295

ISL6295CV

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Battery Management 8LD FUEL GAUGE FOR BATTERY MONITORING
Lifecycle:
New from this manufacturer.
Delivery:
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