10
Application Information
Bypassing and PC Board Layout
The HCPL-0708 optocoupler is extremely easy to use. No
external interface circuitry is required because the HCPL-
0708 uses high-speed CMOS IC technology allowing
CMOS logic to be connected directly to the inputs and
outputs.
Figure 6. Recommended printed circuit board layout.
Figure 7. Recommended printed circuit board layout.
Propagation Delay, Pulse-Width Distortion and Propagation
Delay Skew
Propagation Delay is a gure of merit which describes
how quickly a logic signal propagates through a sys-
tem. The propagation delay from low to high (t
PLH
) is the
amount of time required for an input signal to propagate
to the output, causing the output to change from low
Figure 8.
INPUT
t
PLH
t
PHL
OUTPUT
I
F
V
O
10%
90%90%
10%
V
OH
V
OL
0 mA
50%
12 mA
2.5 V CMOS
7
5
6
8
2
3
4
1
GND
C
NC
V
DD
V
O
I
F
XXX
YWW
C1, C2 = 0.01 µF TO 0.1 µF
V
DD
C2
XXX
YWW
V
O
GND
I
F
C1, C2 = 0.01 µF TO 0.1 µF
As shown in Figure 6, the only external component re-
quired for proper operation is the bypass capacitor. Ca-
pacitor values should be between 0.01 µF and 0.1 µF. For
each capacitor, the total lead length between both ends
of the capacitor and the power-supply pins should not
exceed 20 mm. Figure 7 illustrates the recommended
printed circuit board layout for the HPCL-0708.
to high. Similarly, the propagation delay from high to
low (t
PHL
) is the amount of time required for the input
signal to propagate to the output, causing the output to
change from high to low. See Figure 8.
Figure 9. Propagation delay skew waveform.
Figure 10. Parallel data transmission example.
Propagation delay skew represents the uncertainty of
where an edge might be after being sent through an op-
tocoupler. Figure 10 shows that there will be uncertainty
in both the data and clock lines. It is important that these
two areas of uncertainty not overlap, otherwise the clock
signal might arrive before all of the data outputs have
settled, or some of the data outputs may start to change
before the clock signal has arrived. From these consider-
ations, the absolute minimum pulse width that can be sent
Pulse-width distortion (PWD) is the dierence between
t
PHL
and t
PLH
and often determines the maximum data
rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by the
minimum pulse width (in ns) being transmitted. Typical-
ly, PWD on the order of 20 - 30% of the minimum pulse
width is tolerable; the exact gure depends on the par-
ticular application.
Propagation delay skew, t
PSK
, is an important parameter
to consider in parallel data applications where synchro-
nization of signals on parallel data lines is a concern. If
the parallel data is being sent through a group of opto-
couplers, dierences in propagation delays will cause the
data to arrive at the outputs of the optocouplers at dier-
ent times. If this dierence in propagation delay is large
enough it will determine the maximum rate at which
parallel data can be sent through the optocouplers.
50%
50%
t
PSK
I
F
V
O
I
F
V
O
2.5 V,
CMOS
2.5 V,
CMOS
DATA
INPUTS
CLOCK
DATA
OUTPUTS
CLOCK
t
PSK
t
PSK
Propagation delay skew is dened as the dierence be-
tween the minimum and maximum propagation delays,
either t
PLH
or t
PHL
, for any given group of optocouplers
which are operating under the same conditions (i.e., the
same drive current, supply voltage, output load, and op-
erating temperature). As illustrated in Figure 9, if the in-
puts of a group of optocouplers are switched either ON
or OFF at the same time, t
PSK
is the dierence between
the shortest propagation delay, either t
PLH
or t
PHL
, and
the longest propagation delay, either t
PLH
or t
PHL
.
As mentioned earlier, t
PSK
can determine the maximum
parallel data transmission rate. Figure 10 is the timing
diagram of a typical parallel data application with both
the clock and data lines being sent through the opto-
couplers. The gure shows data and clock signals at the
inputs and outputs of the optocouplers. In this case the
data is assumed to be clocked o of the rising edge of
the clock.
through optocouplers in a parallel application is twice t
PSK
.
A cautious design should use a slightly longer pulse
width to ensure that any additional uncertainty in the
rest of the circuit does not cause a problem.
The HCPL-0708 optocouplers oer the advantage of
guaranteed specications for propagation delays, pulse-
width distortion, and propagation delay skew over the
recommended temperature and power supply ranges.
12
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV02-0877EN
AV02-0877EN January 8, 2008

HCPL-0708

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
High Speed Optocouplers 15MBd 3750Vrms
Lifecycle:
New from this manufacturer.
Delivery:
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