MAX1121EGK+D Datasheet MAX1121EGK+D, MAX1121EGK+TD | P10-P12

MAX1121

Detailed Description—

Theory of Operation

The MAX1121 uses a fully differential, pipelined archi-

tecture that allows for high-speed conversion, opti-

mized accuracy and linearity, while minimizing power

consumption and die size.

Both positive (INP) and negative/complementary analog

input terminals (INN) are centered around a common-

mode voltage of 1.4V, and accept a differential analog

input voltage swing of ±0.3125V each, resulting in a typi-

cal differential full-scale signal swing of 1.25V

P-P

INP and INN are buffered prior to entering each track-

and-hold (T/H) stage and are sampled when the differen-

tial sampling clock signal transitions high. A 2-bit ADC

following the first T/H stage then digitizes the signal, and

controls a 2-bit digital-to-analog converter (DAC).

Digitized and reference signals are then subtracted,

resulting in a fractional residue signal that is amplified

before it is passed on to the next stage through another

T/H amplifier. This process is repeated until the applied

input signal has successfully passed through all stages

of the 8-bit quantizer. Finally, the digital outputs of all

stages are combined and corrected for in the digital cor-

rection logic to generate the final output code. The result

is a 8-bit parallel digital output word in user-selectable

two’s complement or binary output formats with LVDS-

compatible output levels. See Figure 1 for a more

detailed view of the MAX1121 architecture.

Analog Inputs (INP, INN)

INP and INN are the fully differential inputs of the

MAX1121. Differential inputs usually feature good rejec-

tion of even-order harmonics, which allows for enhanced

AC performance as the signals are progressing through

the analog stages. The MAX1121 analog inputs are self-

biased at a common-mode voltage of 1.4V and allow a

differential input voltage swing of 1.25V

P-P

. Both inputs

are self-biased through 2.2kΩ resistors, resulting in a

typical differential input resistance of 4.4kΩ. It is recom-

mended to drive the analog inputs of the MAX1121 in

AC-coupled configuration to achieve best dynamic per-

formance. See the

AC-Coupled Analog Inputs

section for

a detailed discussion of this configuration.

On-Chip Reference Circuit

The MAX1121 features an internal 1.23V bandgap ref-

erence circuit (Figure 3), which, in combination with an

internal reference-scaling amplifier, determines the full-

scale range of the MAX1121. Bypass REFIO with a

0.1µF capacitor to AGND. To compensate for gain

errors or increase the ADC’s full-scale range, the volt-

age of this bandgap reference can be indirectly adjust-

ed by adding an external resistor (e.g., 100kΩ trim

potentiometer) between REFADJ and AGND or

REFADJ and REFIO. See the

Applications Information

section for a detailed description of this process.

Clock Inputs (CLKP, CLKN)

Designed for a differential LVDS clock input drive, it is

recommended to drive the clock inputs of the MAX1121

with an LVDS-compatible clock to achieve the best

dynamic performance. The clock signal source must be

a high-quality, low phase noise to avoid any degrada-

tion in the noise performance of the ADC. The clock

inputs (CLKP, CLKN) are internally biased to 1.2V,

accept a differential signal swing of 0.2V

P-P

to 1.0V

P-P

1.8V, 8-Bit, 250Msps Analog-to-Digital Converter

with LVDS Outputs for Wideband Applications

10 ______________________________________________________________________________________

AGND

INN

INP

TO COMMON-MODE INPUT

2.2kΩ

TO COMMON-MODE INPUT

2.2kΩ

Figure 2. Simplified Analog Input Architecture

REFERENCE

BUFFER

REFIO

REFADJ

CONTROL LINE TO

DISABLE REFERENCE

BUFFER

ADC FULL-SCALE = REFT - REFB

1kΩ

0.1μF

REFERENCE

SCALING

AMPLIFIER

REFT

REFB

Figure 3. Simplified Reference Architecture

and are usually driven in AC-coupled configuration.

See the

Differential, AC-Coupled Clock Input

in the

Applications Information

section for more circuit details

on how to drive CLKP and CLKN appropriately.

Although not recommended, the clock inputs also

accept a single-ended input signal.

The MAX1121 also features an internal clock manage-

ment circuit (duty-cycle equalizer) that ensures that the

clock signal applied to inputs CLKP and CLKN is

processed to provide a 50% duty cycle clock signal,

which desensitizes the performance of the converter to

variations in the duty cycle of the input clock source.

Note that the clock duty-cycle equalizer cannot be

turned off externally and requires a minimum clock fre-

quency of >20MHz to work appropriately and accord-

ing to data sheet specifications.

Clock Outputs (DCLKP, DCLKN)

The MAX1121 features a differential clock output, which

can be used to latch the digital output data with an

external latch or receiver. Additionally, the clock output

can be used to synchronize external devices (e.g.,

FPGAs) to the ADC. DCLKP and DCLKN are differential

outputs with LVDS-compatible voltage levels. There is a

2.1ns delay time between the rising (falling) edge of

CLKP (CLKN) and the rising edge of DCLKP (DCLKN).

See Figure 4 for timing details.

MAX1121

1.8V, 8-Bit, 250Msps Analog-to-Digital Converter

with LVDS Outputs for Wideband Applications

______________________________________________________________________________________ 11

INP

INN

D0P/N–D7P/N

ORP/N

CLKP

CLKN

DCLKP

DCLKN

N - 8 N - 7 N N + 1

PDL

N - 7N - 8 N N + 1

N N + 1 N + 8 N + 9

CPDL

LATENCY

N - 1

SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT

CPDL

- t

PDL

CPDL

- t

PDL

~ 0.4 x t

SAMPLE

with t

SAMPLE

= 1 / f

SAMPLE

NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA.

Figure 4. System and Output Timing Diagram

OGND

2.2kΩ 2.2kΩ

Figure 5. Simplified LVDS Output Architecture

MAX1121

Divide-by-2 Clock Control (CLKDIV)

The MAX1121 offers a clock control line (CLKDIV),

which supports the reduction of clock jitter in a system.

Connect CLKDIV to OGND to enable the ADC’s internal

divide-by-2 clock divider. Data is now updated at one-

half the ADC’s input clock rate. CLKDIV has an internal

pulldown resistor and can be left open for applications

that only operate with update rates one-half of the con-

verter’s sampling rate. Connecting CLKDIV to OV

allows data to be updated at the speed of the ADC input

clock.

System Timing Requirements

Figure 4 depicts the relationship between the clock

input and output, analog input, sampling event, and

data output. The MAX1121 samples on the rising

(falling) edge of CLKP (CLKN). Output data is valid on

the next rising (falling) edge of the DCLKP (DCLKN)

clock, but has an internal latency of nine clock cycles.

Digital Outputs (D0P/N–D7P/N, DCLKP/N,

ORP/N) and Control Input

The digital outputs D0P/N–D7P/N, DCLKP/N, and ORP/N

are LVDS compatible, and data on D0P/N–D7P/N is pre-

sented in either binary or two’s complement format (Table

1). The T/B control line is an LVCMOS-compatible input,

which allows the user to select the desired output for-

mat. Pulling T/B low outputs data in two’s complement

and pulling it high presents data in offset binary format

on the 10-bit parallel bus. T/B has an internal pulldown

resistor and may be left unconnected in applications

using only two’s complement output format. All LVDS

outputs provide a typical voltage swing of 0.4V around

a common-mode voltage of approximately 1.2V, and

must be terminated at the far end of each transmission

line pair (true and complementary) with 100Ω. The

LVDS outputs are powered from a separate power sup-

ply, which can be operated between 1.7V and 1.9V.

The MAX1121 offers an additional differential output

pair (ORP, ORN) to flag out-of-range conditions, where

out of range is above positive or below negative full

scale. An out-of-range condition is identified with ORP

(ORN) transitioning high (low).

Note: Although differential LVDS reduces single-ended

transients to the supply and ground planes, capacitive

loading on the digital outputs should still be kept as low

as possible. Using LVDS buffers on the digital outputs

of the ADC when driving off-board may improve overall

performance and reduce system timing constraints.

1.8V, 8-Bit, 250Msps Analog-to-Digital Converter

with LVDS Outputs for Wideband Applications

12 ______________________________________________________________________________________

INP ANALOG

VOLTAGE LEVEL

INN ANALOG

VOLTAGE LEVEL

OUT-OF-RANGE

ORP (ORN)

BINARY

DIGITAL OUTPUT CODE

(D7–D0)

TWO’S COMPLEMENT

DIGITAL OUTPUT CODE

(D7–D0)

> V

+ 0.3125V < V

- 0.3125V 1 (0)

1111 1111

(exceeds positive full scale,

OR set)

0111 1111

(exceeds positive full scale,

OR set)

+ 0.3125V V

- 0.3125V 0 (1)

1111 1111

(represents positive full

scale)

0111 1111

(represents positive full

scale)

0 (1)

1000 0000 or

0111 1111

(represents midscale)

0000 0000 or

1111 1111

(represents midscale)

- 0.3125V V

+ 0.3125V 0 (1)

0000 0000

(represents negative full

scale)

1000 0000

(represents negative full

scale)

< V

- 0.3125V > V

+ 0.3125V 1 (0)

0000 0000

(exceeds negative full scale,

OR set)

1000 0000

(exceeds negative full scale,

OR set)

Table 1. MAX1121 Digital Output Coding

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

MAX1121EGK+D

Mfr. #:

Buy MAX1121EGK+D

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications

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MAX1121EGK+D

MAX1121EGK+D

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