MAX1121
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= OV
CC
= 1.8V, V
AGND
= V
OGND
= 0, f
SAMPLE
= 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential R
L
= 100Ω ±1%, C
L
= 5pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. ≥ +25°C
guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Offset Voltage OV
OS
1.125 1.310 V
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)
Digital Input Voltage Low V
IL
0.2 x
AV
CC
V
Digital Input Voltage High V
IH
0.8 x
AV
CC
V
TIMING CHARACTERISTICS
CLK to Data Propagation Delay t
PDL
Figure 4 1.5 ns
CLK to DCLK Propagation Delay t
CPDL
Figure 4 2.85 ns
Data Valid to DCLK Rising Edge
t
CPDL
-
t
PDL
Figure 4 (Note 2) 0.92 1.35 1.86 ns
LVDS Output Rise-Time t
RISE
20% to 80%, C
L
= 5pF 460 ps
LVDS Output Fall-Time t
FALL
20% to 80%, C
L
= 5pF 460 ps
Output Data Pipeline Delay t
LATENCY
8
Clock
cycles
POWER REQUIREMENTS
Analog Supply Voltage Range AV
CC
1.70 1.80 1.90 V
Digital Supply Voltage Range OV
CC
1.70 1.80 1.90 V
Analog Supply Current
I
AVCC
f
IN
= 100MHz 220 290 mA
Digital Supply Current I
OVCC
f
IN
= 100MHz 45 75 mA
Total Power Dissipation P
DISS
f
IN
= 100MHz 477 657 mW
Offset 1.6 mV/V
Power-Supply Rejection Ratio
(Note 3)
PSRR
Gain 1.9 %FS/V
Note 1: Static linearity and offset parameters are computed from a best-fit straight line through the code transition points. The full-
scale range is defined as 1023 x slope of the line.
Note 2: Parameter guaranteed by design and characterization; T
A
= T
MIN
to T
MAX
.
Note 3: PSRR is measured with both analog and digital supplies connected to the same potential.
