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M27C160 Summary description
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Figure 3. DIP Connections
Figure 4. SO Connections
G
Q0
Q8
A3
A0
E
V
SS
A2
A1
A13
V
SS
A14
A15
Q7
A12
A16
BYTEV
PP
Q15A-1
Q5Q2
Q3
V
CC
Q11
Q4
Q14
A9
A8A17
A4
A18 A19
A7
AI00740
M27C160
8
1
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
20
19
18
17
Q1
Q9
A6
A5
Q6
Q13
42
39
38
37
36
35
34
33
A11
A10
Q10
21
Q12
40
41
G
Q0
Q8
A3
A0
E
V
SS
A2
A1
A13
V
SS
A14
A15
Q7
A12
A16
BYTEV
PP
Q15A-1
Q5Q2
Q3
V
CC
Q11
Q4
Q14
A9
A19A18
A4
NC NC
A7
AI01264
M27C160
8
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
2322
20
19
18
17Q1
Q9
A6
A5
Q6
Q13
44
39
38
37
36
35
34
33
A11
A10
Q10
21
Q12
40
43
1
42
41
A17 A8
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Device description M27C160
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2 Device description
Table 2 lists the operating modes of the M27C160. A single power supply is required in the
read mode. All inputs are TTL compatible except for V
PP
and 12V on A9 for the Electronic
Signature.
Note: X = V
IH
or V
IL
, V
ID
= 12V ± 0.5V.
2.1 Read mode
The M27C160 has two organisations, Word-wide and Byte-wide. The organisation is
selected by the signal level on the BYTE
V
PP
pin. When BYTEV
PP
is at V
IH
the Word-wide
organisation is selected and the Q15A–1 pin is used for Q15 Data Output. When the
BYTE
V
PP
pin is at V
IL
the Byte-wide organisation is selected and the Q15A–1 pin is used for
the Address Input A–1. When the memory is logically regarded as 16 bit wide, but read in
the Byte-wide organisation, then with A–1 at V
IL
the lower 8 bits of the 16 bit data are
selected and with A–1 at V
IH
the upper 8 bits of the 16 bit data are selected.
The M27C160 has two control functions, both of which must be logically active in order to
obtain data at the outputs. In addition the Word-wide or Byte- wide organisation must be
selected.
Chip Enable (E
) is the power control and should be used for device selection. Output Enable
(G
) is the output control and should be used to gate data to the output pins independent of
device selection. Assuming that the addresses are stable, the address access time (t
AVQV
)
is equal to the delay from E
to output (t
ELQV
). Data is available at the output after a delay of
t
GLQV
from the falling edge of G, assuming that E has been low and the addresses have
been stable for at least t
AVQV
-t
GLQV
.
2.2 Standby mode
The M27C160 has a standby mode which reduces the active current from 50mA to 100µA.
The M27C160 is placed in the standby mode by applying a CMOS high signal to the E
input.
Table 2. Operating Modes
Mode E G BYTEV
PP
A9 Q15A–1 Q8-Q14 Q7-Q0
Read Word-wide V
IL
V
IL
V
IH
X Data Out Data Out Data Out
Read Byte-wide Upper V
IL
V
IL
V
IL
XV
IH
Hi-Z Data Out
Read Byte-wide Lower V
IL
V
IL
V
IL
XV
IL
Hi-Z Data Out
Output Disable V
IL
V
IH
X X Hi-Z Hi-Z Hi-Z
Program V
IL
Pulse V
IH
V
PP
X Data In Data In Data In
Verify V
IH
V
IL
V
PP
X Data Out Data Out Data Out
Program Inhibit V
IH
V
IH
V
PP
X Hi-Z Hi-Z Hi-Z
Standby V
IH
X X X Hi-Z Hi-Z Hi-Z
Electronic Signature V
IL
V
IL
V
IH
V
ID
Code Codes Codes
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M27C160 Device description
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When in the standby mode, the outputs are in a high impedance state, independent of the G
input.
2.3 Two-line output control
Because EPROMs are usually used in larger memory arrays, this product features a 2-line
control function which accommodates the use of multiple memory connection. The two line
control function allows:
the lowest possible memory power dissipation,
complete assurance that output bus contention will not occur.
For the most efficient use of these two control lines, E
should be decoded and used as the
primary device selecting function, while G
should be made a common connection to all
devices in the array and connected to the READ
line from the system control bus. This
ensures that all deselected memory devices are in their low power standby mode and that
the output pins are only active when data is required from a particular memory device.
2.4 System considerations
The power switching characteristics of Advanced CMOS EPROMs require careful
decoupling of the supplies to the devices. The supply current I
CC
has three segments of
importance to the system designer: the standby current, the active current and the transient
peaks that are produced by the falling and rising edges of E
.
The magnitude of the transient current peaks is dependent on the capacitive and inductive
loading of the device outputs. The associated transient voltage peaks can be suppressed by
complying with the two line output control and by properly selected decoupling capacitors. It
is recommended that a 0.1µF ceramic capacitor is used on every device between V
CC
and
V
SS
. This should be a high frequency type of low inherent inductance and should be placed
as close as possible to the device. In addition, a 4.7µF electrolytic capacitor should be used
between V
CC
and V
SS
for every eight devices.
This capacitor should be mounted near the power supply connection point. The purpose of
this capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.
2.5 Programming
When delivered (and after each erasure for UV EPROM), all bits of the M27C160 are in the
'1' state. Data is introduced by selectively programming '0's into the desired bit locations.
Although only '0's will be programmed, both '1's and '0's can be present in the data word.
The only way to change a '0' to a '1' is by die exposure to ultraviolet light (UV EPROM). The
M27C160 is in the programming mode when V
PP
input is at 12.5V, G is at V
IH
and E is
pulsed to V
IL
. The data to be programmed is applied to 16 bits in parallel to the data output
pins. The levels required for the address and data inputs are TTL. V
CC
is specified to be
6.25V ± 0.25V.
2.6 Presto III programming algorithm
The Presto III Programming Algorithm allows the whole array to be programed with a
guaranteed margin in a typical time of 52.5 seconds. Programming with Presto III consists of

M27C160-100B1

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
EPROM 2Mx8 or 1Mx16 100ns
Lifecycle:
New from this manufacturer.
Delivery:
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