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P89LV51RC2FBC,557

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P76
P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 37 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Therefore when Timer 2 is in
use as a baud rate generator, T2EX can be used as an additional external interrupt, if
needed.
When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2
and TL2. Under these conditions, a read or write of TH2 or TL2 may not be accurate. The
RCAP2 registers may be read, but should not be written to, because a write might overlap
a reload and cause write and/or reload errors. The timer should be turned off (clear TR2)
before accessing the Timer 2 or RCAP2 registers. Table 24 shows commonly used baud
rates and how they can be obtained from Timer 2.
6.5.5 Summary of baud rate equations
Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2(P1.0)
the baud rate is:
Baud rate = Timer 2 overflow rate / 16
If Timer 2 is being clocked internally, the baud rate is:
Baud rate = f
osc
/ (16 × (65536 − (RCAP2H, RCAP2L)))
Where f
osc
= oscillator frequency
To obtain the reload value for RCAP2H and RCAP2L, the above equation can be rewritten
as:
RCAP2H, RCAP2L = 65536 − f
osc
/ (16 × baud rate)
6.6 UART
The UART operates in all standard modes. Enhancements over the standard 80C51
UART include Framing Error detection, and automatic address recognition.
6.6.1 Mode 0
Serial data enters and exits through RXD, and TXD outputs the shift clock. Only 8 bits are
transmitted or received, LSB first. The baud rate is fixed at
1
⁄
6
of the CPU clock frequency.
The UART is configured to operate in this mode and outputs serial clock on TXD line no
matter whether it sends or receives data on the RXD line.
Table 24. Timer 2 generated commonly used baud rates
Rate Oscillator frequency Timer 2
RCAP2H RCAP2L
750 kBd 12 MHz FF FF
19.2 kBd 12 MHz FF D9
9.6 kBd 12 MHz FF B2
4.8 kBd 12 MHz FF 64
2.4 kBd 12 MHz FE C8
600 Bd 12 MHz FB 1E
220 Bd 12 MHz F2 AF
600 Bd 6 MHz FD 8F
220 Bd 6 MHz F9 57
P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 38 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
6.6.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logical 0), 8
data bits (LSB first), and a stop bit (logical 1). When data is received, the stop bit is stored
in RB8 in Special Function Register SCON. The baud rate is variable and is determined
by the Timer
1
⁄
2
overflow rate.
6.6.3 Mode 2
11 bits are transmitted (through TXD) or received (through RXD): start bit (logical 0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). When data is
transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or (e.g. the
parity bit (P, in the PSW) could be moved into TB8). When data is received, the 9th data
bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The
baud rate is programmable to either
1
⁄
16
or
1
⁄
32
of the CPU clock frequency, as determined
by the SMOD1 bit in PCON.
6.6.4 Mode 3
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logical 0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). In fact, mode 3
is the same as mode 2 in all respects except baud rate. The baud rate in mode 3 is
variable and is determined by the Timer
1
⁄
2
overflow rate.
Table 25. SCON - Serial port control register (address 98H) bit allocation
Bit addressable; reset value: 00H.
Bit 7 6 5 4 3 2 1 0
Symbol SM0/FE SM1 SM2 REN TB8 RB8 TI RI
Table 26. SCON - Serial port control register (address 98H) bit descriptions
Bit Symbol Description
7 SM0/FE The usage of this bit is determined by SMOD0 in the PCON register. If
SMOD0 = 0, this bit is SM0, which with SM1, defines the serial port
mode. If SMOD0 = 1, this bit is FE (Framing Error). FE is set by the
receiver when an invalid stop bit is detected. Once set, this bit cannot
be cleared by valid frames but can only be cleared by software. (Note:
It is recommended to set up UART mode bits SM0 and SM1 before
setting SMOD0 to ‘1’.)
6 SM1 With SM0, defines the serial port mode (see
Table 27).
5 SM2 Enables the multiprocessor communication feature in modes 2 and 3.
In mode 2 or 3, if SM2 is set to ‘1’, then Rl will not be activated if the
received 9th data bit (RB8) is ‘0’. In mode 1, if SM2 = 1 then RI will not
be activated if a valid stop bit was not received. In mode 0, SM2 should
be ‘0’.
4 REN Enables serial reception. Set by software to enable reception. Clear by
software to disable reception.
3 TB8 The 9th data bit that will be transmitted in modes 2 and 3. Set or clear
by software as desired.
P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 39 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
6.6.5 Framing error
Framing error (FE) is reported in the SCON.7 bit if SMOD0 (PCON.6) = 1. If SMOD0 = 0,
SCON.7 is the SM0 bit for the UART, it is recommended that SM0 is set up before SMOD0
is set to ‘1’.
6.6.6 More about UART mode 1
Reception is initiated by a detected 1-to-0 transition at RXD. For this purpose RXD is
sampled at a rate of 16 times whatever baud rate has been established. When a transition
is detected, the divide-by-16 counter is immediately reset to align its rollovers with the
boundaries of the incoming bit times.
The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th
counter states of each bit time, the bit detector samples the value of RXD. The value
accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise
rejection. If the value accepted during the first bit time is not 0, the receive circuits are
reset and the unit goes back to looking for another 1-to-0 transition. This is to provide
rejection of false start bits. If the start bit proves valid, it is shifted into the input shift
register, and reception of the rest of the frame will proceed.
The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the
following conditions are met at the time the final shift pulse is generated: (a) RI = 0, and
(b) either SM2 = 0, or the received stop bit = 1.
If either of these two conditions is not met, the received frame is irretrievably lost. If both
conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is
activated.
6.6.7 More about UART modes 2 and 3
Reception is performed in the same manner as in mode 1.
2 RB8 In modes 2 and 3, is the 9th data bit that was received. In mode 1, if
SM2 = 0, RB8 is the stop bit that was received. In mode 0, RB8 is
undefined.
1 TI Transmit interrupt flag. Set by hardware at the end of the 8th bit time in
mode 0, or at the stop bit in the other modes, in any serial transmission.
Must be cleared by software.
0 RI Receive interrupt flag. Set by hardware at the end of the 8th bit time in
mode 0, or approximately halfway through the stop bit time in all other
modes. (See SM2 for exceptions). Must be cleared by software.
Table 27. SCON - Serial port control register (address 98H) SM0/SM1 mode definitions
SM0, SM1 UART mode Baud rate
0 0 0: shift register CPU clock / 6
0 1 1: 8-bit UART variable
1 0 2: 9-bit UART CPU clock / 32 or CPU
clock / 16
1 1 3: 9-bit UART variable
Table 26. SCON - Serial port control register (address 98H) bit descriptions
…continued
Bit Symbol Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P76

P89LV51RC2FBC,557

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Buy P89LV51RC2FBC,557
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 32KB FLASH 44TQFP
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