P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 40 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the
following conditions are met at the time the final shift pulse is generated: (a) RI = 0, and
(b) either SM2 = 0, or the received 9th data bit = 1.
If either of these conditions is not met, the received frame is irretrievably lost, and RI is not
set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data
bits go into SBUF.
6.6.8 Multiprocessor communications
UART modes 2 and 3 have a special provision for multiprocessor communications. In
these modes, 9 data bits are received or transmitted. When data is received, the 9th bit is
stored in RB8. The UART can be programmed so that when the stop bit is received, the
serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit
SM2 in SCON. One way to use this feature in multiprocessor systems is as follows:
When the master processor wants to transmit a block of data to one of several slaves, it
first sends out an address byte which identifies the target slave. An address byte differs
from a data byte in a way that the 9th bit is ‘1’ in an address byte and ‘0’ in the data byte.
With SM2 = 1, no slave will be interrupted by a data byte, i.e. the received 9th bit is ‘0’.
However, an address byte having the 9th bit set to ‘1’ will interrupt all slaves, so that each
slave can examine the received byte and see if it is being addressed or not. The
addressed slave will clear its SM2 bit and prepare to receive the data (still 9 bits long) that
follow. The slaves that weren’t being addressed leave their SM2 bits set and ignore the
subsequent data bytes.
SM2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop
bit, although this is better done with the Framing Error flag. When the UART receives data
in mode 1 and SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is
received.
6.6.9 Automatic address recognition
Automatic Address Recognition is a feature which allows the UART to recognize certain
addresses in the serial bit stream by using hardware to make the comparisons. This
feature saves a great deal of software overhead by eliminating the need for the software to
examine every serial address which passes by the serial port. This feature is enabled for
the UART by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3,
the Receive Interrupt flag (RI) will be automatically set when the received byte contains
either the ‘Given’ address or the ‘Broadcast' address. The 9 bit mode requires that the 9th
information bit is a ‘1’ to indicate that the received information is an address and not data.
Using the Automatic Address Recognition feature allows a master to selectively
communicate with one or more slaves by invoking the Given slave address or addresses.
All of the slaves may be contacted by using the Broadcast address. Two Special Function
Registers are used to define the slave’s address, SADDR, and the address mask,
SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits
are ‘don’t care’. The SADEN mask can be logically ANDed with the SADDR to create the
‘Given’ address which the master will use for addressing each of the slaves. Use of the
Given address allows multiple slaves to be recognized while excluding others.
This device uses the methods presented in Figure 15 to determine if a ‘Given’ or
‘Broadcast’ address has been received or not.
P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 41 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
The following examples help to show the versatility of this scheme.
Example 1, slave 0:
(4)
Example 2, slave 1:
(5)
In the above example value SADDR is the same and the SADEN data is used to
differentiate between the two slaves. Slave 0 requires a ‘0’ in bit 0 and it ignores bit 1.
Slave 1 requires a ‘0’ in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be
1100 0010 since slave 1 requires a ‘0’ in bit 1. A unique address for slave 1 would be 1100
0001 since a ‘1’ in bit 0 will exclude slave 0. Both slaves can be selected at the same time
by an address which has bit0=0(forslave0)andbit1=0(forslave1).Thus, both could
be addressed with 1100 0000.
Fig 15. Schemes used by the UART to detect ‘given’ and ‘broadcast’ addresses when multiprocessor
communications is enabled
002aaa527
rx_byte(7)
saddr(7)
saden(7)
rx_byte(0)
saddr(0)
.
.
.
given_address_match
logic used by UART to detect 'given address' in received data
saddr(7)
saden(7)
rx_byte(7)
saddr(0)
saden(0)
rx_byte(0)
broadcast_address_match
logic used by UART to detect 'given address' in received data
saden(0)
.
.
.
SADDR = 1100 0000
SADEN = 1111 1101
Given = 1100 00X0
----------------------------------------------------
SADDR = 1100 0000
SADEN = 1111 1110
Given = 1100 000X
----------------------------------------------------
P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 42 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
In a more complex system the following could be used to select slaves 1 and 2 while
excluding slave 0:
Example 1, slave 0:
(6)
Example 2, slave 1:
(7)
Example 3, slave 2:
(8)
In the above example the differentiation among the 3 slaves is in the lower 3 address bits.
Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1
requires that bit1=0 and it can be uniquely addressed by 1110 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude
Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2.
The Broadcast Address for each slave is created by taking the logical OR of SADDR and
SADEN. Zeros in this result are treated as don’t-cares. In most cases, interpreting the
don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR
and SADEN are loaded with 0s. This produces a given address of all ‘don’t cares’ as well
as a Broadcast address of all ‘don’t cares'. This effectively disables the Automatic
Addressing mode and allows the microcontroller to use standard UART drivers which do
not make use of this feature.
6.7 SPI
6.7.1 SPI features
Master or slave operation
10 MHz bit frequency (maximum)
LSB first or MSB first data transfer
Four programmable bit rates
End of transmission (SPIF)
Write collision flag protection (WCOL)
Wake-up from Idle mode (slave mode only)
6.7.2 SPI description
The SPI allows high-speed synchronous data transfer between the
P89LV51RB2/RC2/RD2 and peripheral devices or between several
P89LV51RB2/RC2/RD2 devices. Figure 16 shows the correspondence between master
SADDR = 1100 0000
SADEN = 1111 1001
Given = 1100 0XX0
----------------------------------------------------
SADDR = 1110 0000
SADEN = 1111 1010
Given = 1110 0X0X
----------------------------------------------------
SADDR = 1100 0000
SADEN = 1111 1100
Given = 1100 00XX
----------------------------------------------------

P89LV51RC2FBC,557

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 32KB FLASH 44TQFP
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