Philips Semiconductors Preliminary data
P87LPC769
Low power, low price, low pin count (20 pin)
microcontroller with 4 kB OTP 8-bit A/D, and DAC
2002 Mar 12
25
BIT SYMBOL FUNCTION
P2M1.7 P2S When P2S = 1, this bit enables Schmitt trigger inputs on Port 2.
P2M1.6 P1S When P1S = 1, this bit enables Schmitt trigger inputs on Port 1.
P2M1.5 P0S When P0S = 1, this bit enables Schmitt trigger inputs on Port 0.
P2M1.4 ENCLK When ENCLK is set and the P87LPC769 is configured to use the on-chip RC oscillator, a clock
output is enabled on the X2 pin (P2.0). Refer to the Oscillator section for details.
P2M1.3 ENT1 When set, the P.7 pin is toggled whenever Timer 1 overflows. The output frequency is therefore
one half of the Timer 1 overflow rate. Refer to the Timer/Counters section for details.
P2M1.2 ENT0 When set, the P1.2 pin is toggled whenever Timer 0 overflows. The output frequency is therefore
one half of the Timer 0 overflow rate. Refer to the Timer/Counterssection for details.
P2M1.1, P2M1.0 These bits, along with the matching bits in the P2M2 register, control the output configuration of
P2.1 and P2.0 respectively, as shown in Table 4.
(P2M1.0)
SU01373
(P2M1.1)ENT0ENT1ENCLKP0SP1SP2S
01234567
P2M1
Reset Value: 00h
Not Bit Addressable
Address: A4h
Figure 16. Port 2 Mode Register 1 (P2M1)
Keyboard Interrupt (KBI)
The Keyboard Interrupt function is intended primarily to allow a
single interrupt to be generated when any key is pressed on a
keyboard or keypad connected to specific pins of the P87LPC769,
as shown in Figure 17. This interrupt may be used to wake up the
CPU from Idle or Power Down modes. This feature is particularly
useful in handheld, battery powered systems that need to carefully
manage power consumption yet also need to be convenient to use.
The P87LPC769 allows any or all pins of port 0 to be enabled to
cause this interrupt. Port pins are enabled by the setting of bits in
the KBI register, as shown in Figure 18. The Keyboard Interrupt Flag
(KBF) in the AUXR1 register is set when any enabled pin is pulled
low while the KBI interrupt function is active. An interrupt will
generated if it has been enabled. Note that the KBF bit must be
cleared by software.
Due to human time scales and the mechanical delay associated with
keyswitch closures, the KBI feature will typically allow the interrupt
service routine to poll port 0 in order to determine which key was
pressed, even if the processor has to wake up from Power Down
mode. Refer to the section on Power Reduction Modes for details.
Philips Semiconductors Preliminary data
P87LPC769
Low power, low price, low pin count (20 pin)
microcontroller with 4 kB OTP 8-bit A/D, and DAC
2002 Mar 12
26
SU01163
KBF (KBI INTERRUPT)
EKB
(FROM IEN1 REGISTER)
P0.7
KBI.7
P0.6
KBI.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
KBI.5
KBI.4
KBI.3
KBI.2
KBI.1
KBI.0
Figure 17. Keyboard Interrupt
BIT SYMBOL FUNCTION
KBI.7 KBI.7 When set, enables P0.7 as a cause of a Keyboard Interrupt.
KBI.6 KBI.6 When set, enables P0.6 as a cause of a Keyboard Interrupt.
KBI.5 KBI.5 When set, enables P0.5 as a cause of a Keyboard Interrupt.
KBI.4 KBI.4 When set, enables P0.4 as a cause of a Keyboard Interrupt.
KBI.3 KBI.3 When set, enables P0.3 as a cause of a Keyboard Interrupt.
KBI.2 KBI.2 When set, enables P0.2 as a cause of a Keyboard Interrupt.
KBI.1 KBI.1 When set, enables P0.1 as a cause of a Keyboard Interrupt.
KBI.0 KBI.0 When set, enables P0.0 as a cause of a Keyboard Interrupt.
Note: the Keyboard Interrupt must be enabled in order for the settings of the KBI register to be effective. The interrupt flag
(KBF) is located at bit 7 of AUXR1.
KBI.0
SU01164
KBI.1KBI.2KBI.3KBI.4KBI.5KBI.6KBI.7
01234567
KBI
Reset Value: 00h
Not Bit Addressable
Address: 86h
Figure 18. Keyboard Interrupt Register (KBI)
Philips Semiconductors Preliminary data
P87LPC769
Low power, low price, low pin count (20 pin)
microcontroller with 4 kB OTP 8-bit A/D, and DAC
2002 Mar 12
27
Oscillator
The P87LPC769 provides several user selectable oscillator options,
allowing optimization for a range of needs from high precision to
lowest possible cost. These are configured when the EPROM is
programmed. Basic oscillator types that are supported include: low,
medium, and high speed crystals, covering a range from 20 kHz to
10 MHz; ceramic resonators; and on-chip RC oscillator.
Low Frequency Oscillator Option
This option supports an external crystal in the range of 20 kHz to 100 kHz.
Table 6 shows capacitor values that may be used with a quartz crystal in this mode.
Table 6. Recommended oscillator capacitors for use with the low frequency oscillator option
Oscillator
V
DD
= 4.5 to 5.5 V
Frequency
Lower Limit Optimal Value Upper Limit
20 kHz 33 pF 33 pF 47 pF
32 kHz 33 pF 33 pF 47 pF
100 kHz 15 pF 15 pF 33 pF
Medium Frequency Oscillator Option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.
Table 7 shows capacitor values that may be used with a quartz crystal in this mode.
Table 7. Recommended oscillator capacitors for use with the medium frequency oscillator option
Oscillator Freq ency
V
DD
= 4.5 to 5.5 V
Oscillator
Freq
u
ency
Lower Limit Optimal Value Upper Limit
100 kHz 33 pF 33 pF 47 pF
1 MHz 15 pF 15 pF 33 pF
4 MHz 15 pF 15 pF 33 pF
High Frequency Oscillator Option
This option supports an external crystal in the range of 4 to 10 MHz. Ceramic resonators are also supported in this configuration.
Table 8 shows capacitor values that may be used with a quartz crystal in this mode.
Table 8. Recommended oscillator capacitors for use with the high frequency oscillator option
Oscillator
V
DD
= 4.5 to 5.5 V
Frequency
Lower Limit Optimal Value Upper Limit
4 MHz 15 pF 33 pF 68 pF
8 MHz 15 pF 33 pF 47 pF
On-Chip RC Oscillator Option
The on-chip RC oscillator option has a typical frequency of 6 MHz
and can be divided down for slower operation through the use of the
DIVM register. Note that the on-chip oscillator has a ±25% frequency
tolerance and for that reason may not be suitable for use in some
applications. A clock output on the X2/P2.0 pin may be enabled
when the on-chip RC oscillator is used.
External Clock Input Option
In this configuration, the processor clock is input from an external
source driving the X1/P2.1 pin. The rate may be from 0 Hz up to
10 MHz. When the external clock input mode is used, the X2/P2.0 pin
may be used as a standard port pin. A clock output on the X2/P2.0 pin
may be enabled when the external clock input is used.
Clock Output
The P87LPC769 supports a clock output function when either the
on-chip RC oscillator or external clock input options are selected.
This allows external devices to synchronize to the P87LPC769.
When enabled, via the ENCLK bit in the P2M1 register, the clock
output appears on the X2/CLKOUT pin whenever the on-chip
oscillator is running, including in Idle mode. The frequency of the
clock output is 1/6 of the CPU clock rate. If the clock output is not
needed in Idle mode, it may be turned off prior to entering Idle,
saving additional power. The clock output may also be enabled
when the external clock input option is selected.

P87LPC769HD,512

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Microcontrollers - MCU 8-bit Microcontrollers - MCU 80C51 4K/128 OTP ADC
Lifecycle:
New from this manufacturer.
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